Multiple mode input analog controller having standby power supply and absence-of-input sensing

• US 4,005,409 A
• Filed: 03/10/1975
• Issued: 01/25/1977
• Est. Priority Date: 03/10/1975
• Status: Expired due to Term

• Current Assignee: Robertshaw Controls Company (Schneider Electric SE)
• Original Assignee: Robertshaw Controls Company (Schneider Electric SE)
• Inventors: Feuer, Mervyn L.
• Primary Examiner(s): Sloyan, Thomas J.
• Application Number:
  US05/556,999
• Time in Patent Office: 687 Days
• Field of Search: 340/347 DA, 340/347 AD, 340/347 C, 340/147 C, 340/147 MT, 324/99 D, 235/92 MP, 235/151.1, 235/151.11, 235/92 T, 307/64, 307/66
• US Class Current: 341/108
• CPC Class Codes: G05B 15/02 electric

Abstract

A controller produces an analog output signal which can be changed in accordance with digital input instruction signals, such as pulse coded binary signals or duration coded binary signals. A memory circuit is isolated and connected to a standby battery in the event that a main power circuit fails.

Claims

1. A controller circuit comprising

a memory having an input and a plurality of outputs for generating digital signals;

digital-to-analog converting means responsive to the digital signals from the memory for converting the digital signals to an analog signal;

first digital input means responsive to digital input signals for incrementally changing the digital signals in the memory;

second digital input means responsive to digital input signals and including a first oscillator for changing the digital signals in the memory in proportion to the length of the digital input signal;

analog input means including a second oscillator generating a digital signal for changing the digital signals in the memory;

data gating means for selectively connecting one of the first digital input means, the second digital input means and the analog input means to the memory;

main power supply means for the memory, the digital-to-analog converting means, the data gating means, and the input means;

standby power means;

means responsive to failure of the main power means and energized by the standby power means for maintaining power to the memory means and the data gating means;

means operated by the power maintaining means for blocking current flow from the plurality of outputs of the memory; and

means operated by the power maintaining means for disabling input to the memory during failure of the main power supply means by inhibiting the operation of the data gating means, the input disabling means also disabling the first and second oscillators to minimize power drain on the standby power means.

2. A controller circuit as claimed in claim 1 wherein the blocking means includes switch means connected in a line to the digital-to-analog converter in response to operation of the power maintaining means.

3. A controller circuit as claimed in claim 1 further comprising manually controlled input means including a low frequency oscillator which generates a digitial signal which is manually gated to send digital signals to change the digital signals in the memory, the low frequency oscillator being input disabled by the disabling means during failure of the main power means.

4. A controller as claimed in claim 1 wherein the standby power means is a rechargable battery and the power maintaining means includes a resistor connecting the main power means to the battery so that the battery is constantly recharged when the main power means is operative.

5. A controller circuit comprising

a memory including a binary counter having an input, a plurality of first outputs for generating binary output signals, and a second output for producing a signal when the counter is full and when the counter is empty;

digital to analog converting means having a plurality of binary inputs connected to the respective first outputs of the memory, a plurality of input junction transistors having control electrodes connected to the respective binary inputs of the converting means, a plurality of current generators for producing currents having values corresponding to the significance of the binary inputs of the converting means, a signal output, a plurality of current switching means operated by the input transistors for switching current from the respective current sources to the signal output, and a pair of power input terminals for energizing the converting means;

amplifier means connected to the signal output for generating an analog output signal;

first input means responsive to binary input signals and including first gating means having first inputs for receiving the binary input signals, a high frequency oscillator, bias means, a selective connection means for making first and second alternate connections, said first connection being to connect the high frequency oscillator to second inputs of the first gating means whereby the binary input signals gate the pulses from the high frequency oscillator, and said second connection being to connect the bias means to the second inputs of the first gating means whereby the binary input signals pass through the gating means;

second input means responsive to an analog input signal and including a variable oscillator, second gating means having first inputs connected to the variable oscillator, a comparator for sensing a difference between the analog output signal and the analog input signal for selectively operating the second gating means, and means responsive to a difference between the analog input signal and the analog output signal exceeding a predetermined value for operating the variable oscillator at a first rate and, when the difference does not exceed the predetermined value, for operating the variable oscillator at a second rate;

indicating means having an off condition, and first and second on conditions;

means sensing the absence of signals from the first and second gating means for a predetermined duration for changing the indicating means from the first on condition to the second on condition to indicate a failure of the controller to update the analog output signal;

manual control means including a low frequency oscillator, third gating means having first inputs connected to the low frequency oscillator, and switch means selectively controlling second inputs of the third gating means;

summing means responsive to the outputs of the first, second and third gating means;

fourth gating means having inputs from the summing means and an output to the input of the memory;

mode control switch means having an automatic mode position disabling the third gating means and having a manual mode position for disabling the first and second gating means;

said mode control switch means further having means for placing the indicating means in the off condition when the mode control switch is in the manual mode position;

power supply means adapted to be energized by an external power source for generating a main power voltage;

a chargeable standby battery;

means connected to power supply means for energizing a first portion of the controller circuit;

diode means connecting the remaining portion of the controller circuit, including the memory and the fourth gating means, to the power supply means for energizing the remaining portion of the controller circuit;

a resistance connecting the standby battery to the diode means such that the battery is charged by the power supply means and the battery maintains energization on the remaining portion of the controller circuit in the event that there is a loss of external power;

said remaining portion of the controller circuit consisting of complementary metal-oxide-silicon circuitry;

power failure sensing means for sensing the voltage on the battery exceeding the main power voltage;

said fourth gating means having inputs connected to the power failure sensing means and connected to the second output of the memory for disabling the fourth gating means to prevent input signals to the memory in the event of power failure, the counter being full, or the counter being empty;

power control means responsive to the power failure sensing means for disconnecting one of the pair of power input terminals of the converting means and for biasing the other of the pair of power input terminals of the converting means to backbias the junctions of the input transistors.