Wafer scale integration system

• US 4,007,452 A
• Filed: 07/28/1975
• Issued: 02/08/1977
• Est. Priority Date: 07/28/1975
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hoff, Marcian E. Jr.
• Primary Examiner(s): Trafton, David L.
• Application Number:
  US05/599,709
• Time in Patent Office: 561 Days
• Field of Search: 340/173 R, 340/173 SP, 340/173 AM, 357/45, 307/303
• US Class Current: 365/63
• CPC Class Codes: G06F 12/0676 the address being position dependent
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/78 using programmable devices

Abstract

A system and method for interconnecting a plurality of separate memories (on other circuits) on a wafer so as to electrically exclude defective memories and include operative memories. A single discretionary connection is associated with each of the separate memories and such connection is made (or broken) after a memory is tested. In addition to a bidirectional memory bus used for input/output data and addresses, the wafer includes a separate identity bus used to define the memory organization. The identity bus is interconnected by a plurality of incrementers, one associated with each memory. The signal on the identity bus is incremented by useable memories and such signal is compared to an address on the bidirectional memory bus to select memories in an organized manner.

Claims

1. In a semiconductor wafer which includes a plurality of circuit units fabricated on said wafer and a first bus for communicating with said devices an improvement comprising:

a second bus disposed on said wafer for transmitting an identification signal to said units;

circuit means disposed on said wafer and coupled to said second bus for selectively altering said identification signal along said second bus;

whereby said circuit means may provide an identification signal to each useable circuit unit on said wafer.

2. The improvement defined by claim 1 wherein said circuit means comprises means for incrementing a signal.

3. The improvement defined by claim 2 wherein said circuit means comprises means for receiving a serial coded digital signal and for incrementing said signal.

4. The imrovement defined by claim 2 wherein said circuit means comprises means for receiving a digital signal transmitted in parallel form and for incrementing said signal.

5. The improvement defined by claim 2 including a plurality of comparator means each for comparing a signal on said first bus with a signal on said second bus, said comparator means being coupled to said first bus and said second bus.

6. The improvement defined by claim 5 including a plurality of discretionary connection means for providing selective coupling with said circuit means.

7. The improvement defined by claim 6 wherein said plurality of circuit units comprises a plurality of memories.

8. The improvement defined by claim 7 including a plurality of multiplexing means each for sensing a signal on said second bus and for directing information from one of said memories to lines of said first bus.

9. A circuit for electrically organizing a plurality of circuit units a semiconductor substrate where some of said units are useable and others are not useable comprising:

a plurality of incrementing means for either incrementing a signal or transmitting a signal unaltered said incrementing means being disposed on said substrate, and

a bus means disposed on said substrate for interconnecting said incrementing means,

whereby said signal on said bus may be incremented for useable circuit unit thereby providing a source of an identification signal.

10. The circuit defined by claim 9 including a plurality of comparator means for comparing signals on said bus with address signals.

11. The circuit defined by claim 10 including a plurality of discretionary connections for providing electrical paths to at least said incrementing means.

12. The circuit defined by claim 11 wherein said circuit units each comprise a memory.

13. The circuit defined by claim 12 including multiplexing means for distributing data said multiplexing means being coupled to said bus.

14. A circuit for organizing a plurality of memories on a semiconductor wafer where some of said memories are operable and others inoperable comprising:

an address and data bus disposed on said wafer,

a plurality of gates for selectively coupling said address and data bus to said memories, said gates being disposed on said wafer,

an identity bus disposed on said wafer, said bus including a plurality of incrementing means disposed along said identity bus,

a plurality of comparator means each for comparing signals on said identity bus with signals on said address and data bus and for providing a signal to one of said memories, each said comparator means being coupled to said identity bus, and said address and data bus to a different one of said memories,

a plurality of data distribution means, each being coupled to said identity bus, said address and data bus and to a different one of said memories, said distribution means for sensing a signal on said identity bus and for directing data to said address and data bus as a function of said sensed signals,

whereby incremented signals along said identity bus provides unique information to each useable memory thereby organizing the useable memories in a memory system.

15. The circuit defined by claim 14 including a plurality of discretionary connections for coupling power to selected incrementing means and gates.

16. The circuit defined by claim 15 wherein said discretionary connections also couples power to operable memories.

17. The circuit defined by claim 14 wherein at least one of said address and data bus, and identity bus includes a main bus and a secondary bus and a discretionary connection for coupling said main bus to said secondary bus.

18. The circuit defined by claim 17 wherein said secondary bus is coupled by a discretionary connection to a plurality of branch busses and wherein said memories are coupled to said branch busses.

19. A semiconductor wafer integration circuit disposed on a wafer with a plurality of other circuit units comprising:

a main bus,

at least one second bus,

discretionary bus connection means coupled to said main bus and said second bus for selectively permitting coupling of said main bus and said second bus; and

incrementing means disposed along said second bus for selectively incrementing signals along said second bus,

whereby identification information may be developed on said wafer as a function of operable circuit units and where operable busses may be selected for use with operable units.

20. The circuit defined by claim 19 including at least a third bus interconnecting said main bus and said second bus and including discretionary bus connection means for providing a selective coupling between said second bus and said third bus.