Averaging counter

• US 4,009,371 A
• Filed: 03/03/1975
• Issued: 02/22/1977
• Est. Priority Date: 03/03/1975
• Status: Expired due to Term

• Current Assignee: Mcdonnell Douglas Corporation (The Boeing Co.)
• Original Assignee: Mcdonnell Douglas Corporation (The Boeing Co.)
• Inventors: Hamilton, Robert H., Mohr, John L.
• Primary Examiner(s): Thesz, Joseph M.
• Application Number:
  US05/554,750
• Time in Patent Office: 722 Days
• Field of Search: 235/92 VA, 235/92 LG, 235/92 CP, 235/92 DM, 235/92 CC, 328/46
• US Class Current: 377/52
• CPC Class Codes: G04F 10/04 by counting pulses or half-cycles of an ac G04F10/005 takes precedence
• CPC Class Codes: H03K 21/38 Starting, stopping or resetting the counter counters with a base other than a power of two H03K23/48, H03K23/66

Abstract

An averaging counter for measuring the elapsed time between events comprising means whereby counting and adding together can be performed using a single counter such as a binary counter and associated control gating means to make the counter switch from one counting mode to another, said counter being able to count by factors which are not multiples of the basic counter modulus and said counter being able to simultaneously count and average.

Claims

1. Means to control a counter to simultaneously count and average comprising a multi-stage counter of M stages, each stage having input and output connections, said means including control gate means, the inputs of stage 1 through M having connections to said control gate means and the outputs of stages 1 through M-1 having connections to said control gate means, enable/inhibit means including start and stop inputs to enable or inhibit selected counter stages, said gate means and said enable/inhibit means, controlling the counter to cause the counter stages to count at a first preselected counting rate in response to receipt of a start signal at said start input, said enable/inhibit means connecting signals at said stop input thereof to said control gate means to effect a change in the counting rate of the multi-stage counter, said control gate means including means to selectively terminate the counting operation of predetermined counting stages upon receipt of a predetermined number of signals at said stop signal input.

2. The control means define in claim 1 including means to change the counting rate of the multi-stage counter by a predetermined amount upon receipt of each signal at said stop signal input.

3. The control means defined in claim 1 including means to effect a change in the counting rate by an integer (1, 2, 3, . . .) each time a signal is received at said stop signal input.

4. Means to control a counter to enable the counter to average a plurality of signals comprising:

a multi-stage binary counter having a plurality of serially connected binary stages, each stage having an input, a clock input, and an output connection thereto, a first source of input control signals to which said plurality of signals are fed and;

control means for predeterminetly applying input control signals from said first source to input connections of selected stages of the binary counter, said input control signals determining the counting rate of said counter by controlling the response of said stages to clock pulses applied thereto, said control means also predeterminately changing input and output connections between the counter stages to which the input signals from said first source are applied to effect a change in the counting rate, the counter counting clock pulses at a counting rate which depends on how the counter stages have input control signals applied thereto, said means to predeterminately change the input and output connections between counter stages including a gated control circuit.

5. Means to simultaneously accumulate and average the times of arrivals of a plurality of input pulses with respect to a predetermined time comprising:

an averaging counter having a plurality of serially connected stages each having an input, an output, and a clock input for receiving common clock signals, means for enabling/inhibiting selected ones of the inputs of the counter stages to cause said counter to accumulate clock signals at preselected rates, said last named means also including a source of control signal pulses and means responsive to receipt of succeeding input pulses to enable/inhibit the inputs to the counter stages, each succeeding change effecting a change in the clock signal counting rate.

6. The means defined in claim 5 wherein said last named means to enable/inhibit include means to reduce the counting rate by an integer value (1, 2, 3, . . .) each time an input pulse is received.

7. The means defined in claim 5 wherein said last named means to enable/inhibit include a multi-stage bistable control circuit responsive to receipt of said input pulses, and gate circuit means operatively connected between the multi-stage control circuit and the stages of said averaging counter.

8. Means to average the times of arrival of a plurality of signals comprising:

a binary counter having a plurality of serially connected stages each having an input and an output and a clock input, each state of said counter being able to accumulate clock inputs at a rate that is a factor of two compared to the adjacent stages;

means for enabling selected stages of the binary counter to respond to adjacent stages, the stages selected in part determining the rate at which the counter counts the clock signals it receives;

input signal pulses whose times of arrivals after a predetermined time are to be averaged; and

means responsive to receipt of the input signal pulses including means for enabling different combinations of the counter stages to respond to said clock signals to change the counting rate thereof.

9. The means defined in claim 8 wherein the binary counter accumulates increments received at its clock inputs at a lesser rate following receipt of each input signal pulse.

10. The means defined in claim 8 including means to establish an initial counting rate, a start signal establishing said predetermined time and means responsive to receipt of said start signal to establish an initial operative connection of said binary counter stages.

11. The means defined in claim 10 including means responsive to receipt of each input signal pulse to change the connections between the counter stage inputs in a way to reduce the counting rate of the binary counter by a predetermined factor.

12. A counter for counting a plurality of signals and producing the average thereof including:

a control register having a start input, a stop input, a plurality of at least N outputs where N equals the number of signals to be counted and averaged, and logic means to produce N+1 discrete combinations of predetermined control output signals at said plurality of N outputs;

a plurality of 1 through M counting elements each having an input for signals to be counted, a reset input, a complementary pair of outputs, and at least one control input, said counting elements including means responsive to signals at said control inputs to control the counting therewithin; and

a plurality of 1 through M logic gates, each gate having an output connected to the control input of an adjacent counting element and inputs connected to predetermined control signal output signals from said control register, said gates 2 through M each also having input connections to the outputs of the preceding counting elements, whereby said logic gates and control register causes said counting elements to count at N minus the number of signals at said stop input times the signals to be counted so that the accumulation therein is N times the average number of signals to be counted.