Field inversion control for N-channel device integrated circuits

• US 4,011,105 A
• Filed: 09/15/1975
• Issued: 03/08/1977
• Est. Priority Date: 09/15/1975
• Status: Expired due to Term

• Current Assignee: MOS Technology, Inc.
• Original Assignee: MOS Technology, Inc.
• Inventors: Paivinen, John O., Eisenhower, Walter D.
• Primary Examiner(s): Rutledge, L. Dewayne
• Assistant Examiner(s): Davis, J. M.
• Application Number:
  US05/613,537
• Time in Patent Office: 540 Days
• Field of Search: 148/1.5, 148/187
• US Class Current: 438/276
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 27/0883 Combination of depletion and enhancement field effect transistors
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762

Abstract

The field inversion properties of integrated circuits incorporating N-channel MOS devices are improved by using a silicon substrate whose bulk dopant concentration is low, but whose local dopant concentration is high at the field surfaces under the field oxide separating the active surface areas where the individual N-channel MOS devices are formed. The differential doping between surface areas under the field oxide and the active surface areas of the substrate is done by nonselectively ion-implanting boron into the substrate to form a uniform low resistivity layer, removing selected portions of the low resistivity layer to expose the unimplanted, high resistivity substrate and forming the active devices at the unimplanted substrate portions. As an option, the unimplanted surface portion can be doped to an intermediate dopant concentration to improve performance. The remaining pattern of the low resistivity layer is covered with field oxide. The invention allows the use of relatively inexpensive, low dopant concentration substrates to conveniently manufacture high performance N-channel MOS integrated circuits.

Claims

1. A method of making an N-channel MOS integrated circuit structure comprising the steps of:

providing a substrate of a P^--type semiconductor material and forming a uniform thin oxide layer along a major surface of the substrate;

ion-implanting a P-type dopant through the oxide layer to form immediately thereunder a uniform layer of P^+-type semiconductor material extending along said major substrate surface;

removing selected spaced-apart portions of the oxide layer and the underlying P^+-type layer to leave a pattern of unimplanted active areas of the substrate spaced laterally by unremoved fields of oxide and underlying fields of P^+-type material;

forming a uniform thin oxide layer over the active substrate areas and forming a substantially thicker oxide layer over said fields;

ion-implanting a P-type dopant through the thin oxide layer into the active substrate areas to form at said active areas layers of P-type semiconductor material whose resistivity is lower than that of the P^--type substrate and higher than that of the P^+-type fields; and

forming N-channel MOS devices at least at selected ones of said layers of P-type material.

2. A method as in claim 1 wherein each of the steps of forming a thin oxide layer includes forming an oxide layer whose thickness is of the order of 1000 A and wherein the steps of forming the P-type and P^+-type layers comprise forming layers whose thickness is of the order of 1000 A.

3. A method as in claim 1 including the steps of implanting an N-type dopant into selected active areas and forming depletion-type active devices at the last recited active areas.

4. A method of making an integrated circuit structure having N-channel MOS devices disposed along a laterally extending major surface of a high bulk resistivity P-type substrate and laterally spaced from each other by low resistivity P-type surface field areas of said substrate for field inversion control, comprising the steps of:

ion-implanting a selected P-type dopant into a laterally extending major surface of a high bulk resistivity P-type material substrate to form a laterally uniform layer of low resistivity P-type material extending along said major surface of the substrate;

removing selected portions of said layer to form a pattern of active areas of unimplanted substrate surface spaced apart by a pattern of the remaining low resistivity layer portions; and

forming N-channel MOS devices at least at selected ones of said active areas of the substrate, said devices being laterally spaced from each other by field areas formed by said remaining portions of the layer of low resistivity P-type material.

5. A method of making an integrated circuit structure as in claim 4 including the step of forming, prior to forming the MOS devices, a layer of a P-type material at the active areas of the substrate, the resistivity of the last recited layer being lower than that of the high bulk resistivity substrate but higher than that of the low resistivity P-type material layer.

6. A method of making an integrated circuit structure as in claim 5 wherein at least one of the steps of forming the intermediate and low resistivity layers includes ion-implanting a P-type dopant through a thin oxide layer diffusing the implant ions.

7. A method of making a semiconductor material structure comprising the steps of:

providing a semiconductor material substrate of a selected conductivity type and selected resistivity, and forming along a laterally extending major surface thereof a laterally uniform semiconductor material layer of the same conductivity type but of lower resistivity;

removing selected area portions of said layer to form at said substrate surface a pattern of unimplanted active substrate areas separated from each other by the unremoved portions of said layer; and

forming integrated circuit components at said active substrate areas, said components being spaced from each other by fields formed by said unremoved portions of the lower resistivity layer.

8. A method of making a semiconductor material structure as in claim 7 wherein the removing step comprises removing selected area portions of the layer to a selected depth into the substrate to depress the active areas into the substrate.

9. A method of making a semiconductor material structure as in claim 7 including the step of forming at the active substrate areas, prior to forming the integrated circuit components, laterally uniform semiconductor material layers of the same conductivity type as the substrate but of resistivity which is intermediate that of the substrate and said lower resistivity layer.

10. A method of making a semiconductor material structure as in clain 7 wherein the step of forming the low resistivity layer comprises ion-implanting a selected dopant into the semiconductor material through a layer of iondiffusing material.