System to render constant the probability of false alarm in radar signals converted into numerical form
First Claim
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1. Apparatus for obtaining constant false alarm probability in radar signals comprising:
- means to transform analog video signals into M bit digital signals;
a first digital delay block comprising M digital delay lines connected to receive said digital signals and having a central M-bit output and N lateral outputs of M-bits,means for generating a and H-bit binary noise signal;
a second digital delay block comprising H digital delay lines for receiving said binary noise signal and having a central H-bit output and N lateral outputs, each one comprising H-bits;
computing means for generating a signal word corresponding to the value of the M+H bits by processing the N-lateral outputs of the first digital delay line block and by processing the N-lateral outputs from the second digital delay line block; and
comparator means connected to receive the output signal from said computing means and the signals from the central bit outputs of said first digital delay block and said second digital delay block for generating a quantized video signal.
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Abstract
Apparatus for obtaining constant false alarm probability in radar signals comprising a means to transform analog radar signals into digital signals with a quantity of binary numbers high enough to cause the density of probability of the amplitude of the digital radar signal to be maintained at a constant value.
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Citations
3 Claims
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1. Apparatus for obtaining constant false alarm probability in radar signals comprising:
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means to transform analog video signals into M bit digital signals; a first digital delay block comprising M digital delay lines connected to receive said digital signals and having a central M-bit output and N lateral outputs of M-bits, means for generating a and H-bit binary noise signal; a second digital delay block comprising H digital delay lines for receiving said binary noise signal and having a central H-bit output and N lateral outputs, each one comprising H-bits; computing means for generating a signal word corresponding to the value of the M+H bits by processing the N-lateral outputs of the first digital delay line block and by processing the N-lateral outputs from the second digital delay line block; and comparator means connected to receive the output signal from said computing means and the signals from the central bit outputs of said first digital delay block and said second digital delay block for generating a quantized video signal. - View Dependent Claims (2, 3)
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Specification
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Current AssigneeGiovanni Picardi, Tullio Bucciarelli
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Original AssigneeGiovanni Picardi, Tullio Bucciarelli
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InventorsPicardi, Giovanni, Bucciarelli, Tullio
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Primary Examiner(s)Gruber, Felix D.
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Application NumberUS05/528,006Time in Patent Office844 DaysField of Search340/146.2, 235/177, 235/181, 235/150.53, 343/5 DP, 343/7 A, 343/7.7, 343/8US Class Current340/146.2CPC Class CodesG01S 7/2927 by deriving and controlling...
