Logic passing device for automatic railway piloting

• US 4,015,807 A
• Filed: 03/31/1976
• Issued: 04/05/1977
• Est. Priority Date: 04/04/1975
• Status: Expired due to Term

• Current Assignee: Societe Generale de Constructions Electriques et Mecaniques "Alsthom et CIE"
• Original Assignee: Societe Generale de Constructions Electriques et Mecaniques "Alsthom et CIE"
• Inventors: Pontier, Claude, Bourree, Guy
• Primary Examiner(s): Blix, Trygve M.
• Assistant Examiner(s): Eisenzopf, Reinhard J.
• Application Number:
  US05/672,443
• Time in Patent Office: 370 Days
• Field of Search: 246/182 B, 246/187 B, 246/187 C, 246/34 R, 246/40, 246/167 R, 246/177
• US Class Current: 246/187.00B
• CPC Class Codes: B61L 15/0062 On-board target speed calculation or supervision
• CPC Class Codes: B61L 3/225 using separate conductors along the route

Abstract

Logic passing method and device enabling an automatic pilot-driving of trs in the section of track which follows the section occupied by a preceding train. The method consists in determining the rules for allowing and preventing and in implementing them by a logic passing device in which memories are set by first data and activated by second data. Applications: signals on railways or underground systems.

Claims

1. Automatic railway piloting method for a track divided into sections, each section comprising a closed loop circuit fed by an emitter on the group sending out signals whose frequency is variable according to the speed limit other than zero or zero speed which the train must keep to in the said section, the engine of the train being equipped with sensors receiving the said signals and allowing the train to drive at the said speed limit or to stop, in which case, the automatic piloting is changed over to visual driving, the said sections being successively even and odd and having a code of frequencies in the even sections and another code of frequencies in the odd sections corresponding to each speed different from zero and to zero speed, said method comprising establishing only any one of the following transition conditions to give rise to a permission to drive:

For the start-up tripping;

Speeds other than zero, even towards speeds other than zero, odd

Speeds other than zero, odd towards speeds other than zero, even

For subsequent tripping;

Speeds other than zero, even towards speeds other than zero, odd

Speeds other than zero, even towards zero speeds, odd

Speeds other than zero, odd towards speeds other than zero, even

Speeds other than zero, odd towards zero speed, even.

2. Logic passing method according to claim 1, wherein the first data and the second data, namely V ≠

0, even and V ≠

0, odd are memorized respectively in a first memory and a second memory, which are suitable for sending out a signal for permission to drive in compliance with four data items V ≠

0 even, V ≠

0 odd, V0 even, V0 odd when these latter appear after one of the first two in the order shown in claim 1.

3. Logic passing device implementing an automatic railway piloting method comprising a track divided into sections, each section comprising a loop fed by an emitter on the ground sending out signals whose frequency is variable according to the speed limit other than zero or zero speed which the train must keep to in the said section, the engine of the train being equipped with sensors receiving the said signals and allowing the train to drive at the said speed limit or to stop, in which case the automatic piloting is changed over to visual driving the said sections being successively even and odd and having a code of frequencies in the even sections and another code of frequencies in the odd sections corresponding to each speed different from zero and to zero speed such that only any one of the following transition conditions is able to give rise to a permission to drive:

For the start-up tripping;

Speeds other than zero, even towards speeds other than zero, odd Speeds other than zero, odd towards speeds other than zero, even;

For subsequent tripping;

Speeds other than zero, even towards speeds other than zero, odd Speeds other than zero, even towards zero speeds, odd Speeds other than zero, odd towards speeds other than zero, even Speeds other than zero, odd towards zero speed, even;

the first data and the second data namely V ≠

0, even and V ≠

0, odd are memorized respectively in a first memory and a second memory, which are suitable for sending out a signal for permission to drive in compliance with four data items V ≠

0 even, V ≠

0 odd, V0 even, V0 odd when these latter appear after one of the first two in the order shown, said device comprising a first input corresponding to the first data V ≠

0, even connected to a first time delay circuit which is connected on the one hand to one of the inputs of a first OR gate belonging to a first memory constituted by the said first OR gate and by a first AND gate, the output of the said first OR gate being connected to one of the inputs of the said first AND gate and the output of the said first AND gate forming a closed loop circuit with the other input of the said first OR gate and on the other hand, to an input of a third AND gate;

a second input corresponding to the second data V ≠

0, odd connected to a second time delay circuit which is connected on the one hand, to one of the inputs of a second OR gate belonging to a second memory constituted by the said second OR gate and by a second AND gate, the output of the said second OR gate being connected to one of the inputs of the said second AND gate and the output of the said second AND gate forming a closed loop circuit with the other input of the said second OR gate and on the other hand, to an input of a fourth AND gate;

a third input corresponding to the third data V0 even connected to a third time delay circuit which is connected to one of the inputs of a third AND gate whose output is connected to the other input of the said third OR gate whose output is connected to the other input of the said second AND gate;

a fourth input corresponding to the fourth data V0 odd connected to a fourth time delay circuit which is connected to one of the inputs of the said fourth AND gate whose output is connected to the other input of the said fourth OR gate whose output is connected to the other input of the said first AND gate;

a fifth input corresponding to the feed source of the engine connected to one of the inputs of a fifth AND gate belonging to a third memory constituted by a fifth OR gate and by a fifth AND gate, the output of the said fifth AND gate being connected on the one hand, to the other input of the said third AND gate and on the other hand, to the other input of the said fourth AND gate and forming a closed loop circuit with one of the inputs of the said fifth OR gate;

the outputs of the first and second AND gates being connected respectively to each of the inputs of a sixth OR gate whose output is connected on the one hand, to the other input of the said fifth OR gate and on the other hand, to the output terminal of the logic passing device.