System for verifying credit status
First Claim
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1. In a credit status verification system, the combination comprising:
- an on-line real-time computer programmed with data concerning the credit of a bearer of a customer account decimal number including the number of short checks in a particular time period generating high-speed, synchronous output messages in a binary coded digital signal form, said computer generating response-type output messages relating to the credit status of a bearer, line control characters and address characters and poll-type output messages;
converter means for the computer havinga step-down portion to change the output messages from the computer to a slow-speed smaller bit code, asynchronous format, said step down portion including;
a decode logic circuit to receive the output messages from the computer,a flip-flop to receive a set signal from the decode logic circuit and receive a reset signal from the decode logic circuit actuated by an end-of-message character in the output message,a high speed clock to provide high speed timing to output the messages from the computer,a low speed clock to provide low speed timing for the output messages from the computer,a logic network including a first AND gate controlled by said flip-flop and high speed clock, a second AND gate controlled by said flip-flop and low speed clock and an OR gate controlled by said first and second AND gates,an output shift register controlled by said output messages and the output of said OR gate,a character strip control to control the output shift register to remove selected characters from the output message and from the output shift register,and a universal asynchronous receiver-transmitter coupled to the output of said output shift register to convert the output messages from the output shift register to a form that may be transmitted by a modem;
a step-up portion to change the input messages from the terminals to a high-speed larger bit code asynchronous format, said step-up portion including;
a universal asynchronous receiver-transmitter to convert the input messages received from a modem to a form that may be applied to logic circuits,a decode logic circuit to receive the input messages from the universal asynchronous receiver-transmitter,a flip-flop to receive a set signal from the decode logic circuit and a reset signal from the decode logic circuit actuated by an end-of-message character in the input message,a high speed clock to provide high speed timing for input messages,a low speed clock to provide low speed timing for input messages,a logic network including a first AND gate controlled by the flip-flop and high speed clock, a second AND gate controlled by the flip-flop and low speed clock and an OR gate controlled by said first and second AND gates,an input shift register controlled by the output messages from the universal asynchronous receiver-transmitter and the OR gate,a character add control to control the output of the input shift register to add line control characters for the high speed input messages anda character generator coupled to an input shift register to add a character that checks for error;
a telephone line to transmit output messages and transmit input messages;
a first modem coupled between the telephone line and the converter means and a second modem coupled between the telephone line and each of a plurality of interface controllers, each said modem converting digital signals to analog signals and converting analog signals back to digital signals;
each said interface controller for each of said second modems including;
a universal asynchronous receiver-transmitter receiving output messages from one of said second modems,an address recognition shift register receiving output messages from the universal asynchronous receiver-transmitter,an address strap controlling the shift register to recognize an address for one of said terminal units,a poll or response block for distinguishing between a poll-type and a response-type output message,an address decoder having a plurality of outputs with one output to each terminal unit to couple a particular response-type message to a particular of said terminal units,an any inputs ready block responsive to a poll-type output message,a go-ahead generator responsive to a no signal from the any inputs ready block for generating a go-ahead character indicating no response-type messages were sent,an input control receiving data-type input messages from each terminal unit controlled by a yes signal from the any inputs ready block allowing only one input message per poll,an input inquiry assembly register responsive to the output of said input control,an OR gate responsive to the go-ahead generator and the output of the input inquiry assembly register anda universal asynchronous receiver-transmitter responsive to an output from the OR gate and a control for controlling the input inquiry assembly shift register and universal asynchronous receiver-transmitter;
a plurality of input-output terminal units associated with each interface controller for each of said second modems for generating input messages in a binary coded signal form, said input messages including line control character, address character, polling character and data-type messages, each said terminal unit including;
a keyboard with a plurality of depressible keys to enter a selected decimal number,a display register to display the decimal number produced by depressing the keys,an output response register to display a response-type output message received from the computer, anda calculator large scale integrated circuit responsive to a selected decimal number input on said keyboard transmitting said entered decimal number to said display register for storing said entered decimal number in a binary coded form until a certain response-type message is received from said computer, at which time said stored decimal number is automatically transmitted as an input message in a binary coded digital form to said computer.
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Abstract
A credit status verification system and method that affords high flexibility for use by merchants and bankers has a high speed, high capacity, on-line, real time computer which stores data concerning the credit status of the bearer of a particular decimal number, usually a customer bank account number. A plurality of terminal units in stores and/or banks generate input messages in a binary coded digital signal form to be received by the computer, and the computer produces output messages in a binary coded digital signal form to be sent to the terminal units preferably over telephone lines. A polling unit at the computer is used to continuously interrogate the terminal units to see if they are operational and if they have any input messages ready and also recognize poll-type input messages. Address characters with the messages locate the terminals and identify the incoming messages. A converter is used at the computer to step down the speed and change codes for output messages while changing them to asynchronous and to step up the speed and change codes for input messages while changing them back to synchronous. Interface controllers for the terminal units facilitate one controller remote from the computer for a plurality of terminal units, distinguishes between poll-type and response-type messages, and identifies the terminal unit for receipt of the input messages by the computer.
87 Citations
3 Claims
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1. In a credit status verification system, the combination comprising:
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an on-line real-time computer programmed with data concerning the credit of a bearer of a customer account decimal number including the number of short checks in a particular time period generating high-speed, synchronous output messages in a binary coded digital signal form, said computer generating response-type output messages relating to the credit status of a bearer, line control characters and address characters and poll-type output messages; converter means for the computer having a step-down portion to change the output messages from the computer to a slow-speed smaller bit code, asynchronous format, said step down portion including; a decode logic circuit to receive the output messages from the computer, a flip-flop to receive a set signal from the decode logic circuit and receive a reset signal from the decode logic circuit actuated by an end-of-message character in the output message, a high speed clock to provide high speed timing to output the messages from the computer, a low speed clock to provide low speed timing for the output messages from the computer, a logic network including a first AND gate controlled by said flip-flop and high speed clock, a second AND gate controlled by said flip-flop and low speed clock and an OR gate controlled by said first and second AND gates, an output shift register controlled by said output messages and the output of said OR gate, a character strip control to control the output shift register to remove selected characters from the output message and from the output shift register, and a universal asynchronous receiver-transmitter coupled to the output of said output shift register to convert the output messages from the output shift register to a form that may be transmitted by a modem; a step-up portion to change the input messages from the terminals to a high-speed larger bit code asynchronous format, said step-up portion including; a universal asynchronous receiver-transmitter to convert the input messages received from a modem to a form that may be applied to logic circuits, a decode logic circuit to receive the input messages from the universal asynchronous receiver-transmitter, a flip-flop to receive a set signal from the decode logic circuit and a reset signal from the decode logic circuit actuated by an end-of-message character in the input message, a high speed clock to provide high speed timing for input messages, a low speed clock to provide low speed timing for input messages, a logic network including a first AND gate controlled by the flip-flop and high speed clock, a second AND gate controlled by the flip-flop and low speed clock and an OR gate controlled by said first and second AND gates, an input shift register controlled by the output messages from the universal asynchronous receiver-transmitter and the OR gate, a character add control to control the output of the input shift register to add line control characters for the high speed input messages and a character generator coupled to an input shift register to add a character that checks for error; a telephone line to transmit output messages and transmit input messages; a first modem coupled between the telephone line and the converter means and a second modem coupled between the telephone line and each of a plurality of interface controllers, each said modem converting digital signals to analog signals and converting analog signals back to digital signals; each said interface controller for each of said second modems including; a universal asynchronous receiver-transmitter receiving output messages from one of said second modems, an address recognition shift register receiving output messages from the universal asynchronous receiver-transmitter, an address strap controlling the shift register to recognize an address for one of said terminal units, a poll or response block for distinguishing between a poll-type and a response-type output message, an address decoder having a plurality of outputs with one output to each terminal unit to couple a particular response-type message to a particular of said terminal units, an any inputs ready block responsive to a poll-type output message, a go-ahead generator responsive to a no signal from the any inputs ready block for generating a go-ahead character indicating no response-type messages were sent, an input control receiving data-type input messages from each terminal unit controlled by a yes signal from the any inputs ready block allowing only one input message per poll, an input inquiry assembly register responsive to the output of said input control, an OR gate responsive to the go-ahead generator and the output of the input inquiry assembly register and a universal asynchronous receiver-transmitter responsive to an output from the OR gate and a control for controlling the input inquiry assembly shift register and universal asynchronous receiver-transmitter; a plurality of input-output terminal units associated with each interface controller for each of said second modems for generating input messages in a binary coded signal form, said input messages including line control character, address character, polling character and data-type messages, each said terminal unit including; a keyboard with a plurality of depressible keys to enter a selected decimal number, a display register to display the decimal number produced by depressing the keys, an output response register to display a response-type output message received from the computer, and a calculator large scale integrated circuit responsive to a selected decimal number input on said keyboard transmitting said entered decimal number to said display register for storing said entered decimal number in a binary coded form until a certain response-type message is received from said computer, at which time said stored decimal number is automatically transmitted as an input message in a binary coded digital form to said computer. - View Dependent Claims (2, 3)
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Specification
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Current AssigneeCoded Verification Systems Incorporated
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Original AssigneeRichard D. Randolph
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InventorsRandolph, Richard D.
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Primary Examiner(s)Yusko, Donald J.
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Application NumberUS05/441,649Time in Patent Office1,156 DaysField of Search340/152 R, 340/153, 340/149 A, 179/2 CA, 235/61.7 BUS Class Current379/91.01CPC Class CodesG06F 3/147 using display panelsG06Q 10/02 Reservations, e.g. for tick...G06Q 20/4037 Remote solvency checksG07F 7/08 by coded identity card or c...
