D. C. motor control system

• US 4,019,107 A
• Filed: 02/03/1975
• Issued: 04/19/1977
• Est. Priority Date: 02/03/1975
• Status: Expired due to Term

• Current Assignee: Schindler Elevator Corporation (Schindler Holding AG)
• Original Assignee: Reliance Electric Company (ABB Limited)
• Inventors: Oliver, Theodore A., Wilson, James W. A., Dixon, George Scott, Gilbert, Edward O.
• Primary Examiner(s): Dobeck, B.
• Application Number:
  US05/546,201
• Time in Patent Office: 806 Days
• Field of Search: 318/338, 318/493, 318/327, 318/317, 318/332, 318/432
• US Class Current: 388/806
• CPC Class Codes: H02P 7/2985 whereby the speed is regulated by measuring the motor speed and comparing it with a given physical value
• CPC Class Codes: Y10S 388/903 Protective, e.g. voltage or current limit
• CPC Class Codes: Y10S 388/906 Proportional-integral system
• CPC Class Codes: Y10S 388/93 Load or torque

Abstract

A direct current motor control system for generating current command signals to a unidirectional armature controller and a bidirectional field controller. A motor speed command is compared with the actual motor speed to generate a speed error signal. The system generates a current command signal from the average of the speed error signal wherein the current command signal is proportional to the square root of the desired motor torque. The absolute value of the current command signal is the input to the armature controller and the field controller receives the current command signal wherein the polarity of the signal determines the direction of current flow in the field winding for controlling the direction of rotation of the motor.

Claims

1. A control circuit for a direct current shunt field electric motor having a field current controller and an armature current controller, comprising:

a source of a speed command signal for said motor;

a source of a signal representing the actual speed of said motor; and

means responsive to said speed command signal and said actual speed signal for generating current command signals to said field and armature controllers wherein the normalized values of said current command signals are proportional to the square root of the motor torque at the desired motor speed represented by said speed command signal.

2. A control circuit as defined in claim 1 wherein said means for generating current command signals includes summing means responsive to said speed command signal and said actual speed signal for generating a speed error signal;

means responsive to said speed error signal for generating an average speed error signal;

means responsive to said average speed error signal for generating said field current command signal; and

means responsive to said average speed error signal for generating said armature current command signal.

3. A control circuit as defined in claim 2 wherein said speed command signal and said actual speed signal have opposite polarities for the same direction of rotation of said motor and said speed error signal is generated by adding said speed signals together.

4. A control circuit as defined in claim 2 wherein said summing means includes an amplifier having an input connected to said speed command signal source and said actual speed signal source and having an output connected to said means for generating an average speed error signal.

5. A control circuit as defined in claim 2 wherein said means for generating an average speed error signal includes an integrator having an input connected to said summing means and an output connected to said means for generating said field current command signal and connected to said means for generating said armature current command signal.

6. A control circuit as defined in claim 5 wherein said means for generating an average speed error signal includes means for limiting the magnitude of said average speed error signal to a predetermined maximum value.

7. A control circuit as defined in claim 5 including means to selectively connect said integrator input to said integrator output to set said average speed error signal to zero.

8. A control circuit as defined in claim 2 wherein said means for generating said field current command signal includes an amplifier having an input connected to said means for generating an average speed error signal for generating said field command signal.

9. A control circuit as defined in claim 8 wherein said means for generating said field current command signal includes means for limiting the magnitude of said field current command signal to a predetermined maximum value.

10. A control circuit as defined in claim 2 wherein said means for generating said armature current command signal includes means responsive to said average speed error signal for generating a signal representing the absolute value of said average speed error signal.

11. A control circuit as defined in claim 10 wherein said absolute value signal means includes means responsive to said average speed error signal of one polarity for generating a first output signal representing said average speed error signal at a first magnitude with the opposite polarity and responsive to said average speed error signal of the opposite polarity for removing said first output signal;

means responsive to said average speed error signal for generating a second output signal representing said average speed error signal at a second magnitude with the same polarity; and

means responsive to said first and second output signals for generating said armature current command signal.

12. A control circuit as defined in claim 11 wherein said first magnitude is twice as great as said second magnitude.

13. A control circuit as defined in claim 2 including a source of a phase back drive signal and means responsive to said phase back drive signal for generating a signal representing zero armature current to said armature controller.

14. A control circuit as defined in claim 2 including means for generating an armature current command signal at a predetermined minimum value connected to the output of said means for generating an armature current command signal.