Analog-to-digital converter employing common mode rejection circuit
First Claim
1. An analalog-to-digital converter of the single slope detection type comprising:
- a first input terminal for receiving a first input signal formed by the superposition of a common mode noise voltage on a first DC voltage;
a second input terminal for receiving a second input signal formed by the superposition of said common mode noise voltage on a second DC voltage;
ramp generating means coupled to said second input terminal and receiving said second input signal;
said ramp generating means operative to isolate said common mode noise voltage from said second input signal and to develop a ramp reference signal that is modulated by said common mode noise voltage;
a first comparator having a first input connected to said first terminal for receiving said first input signal, a second input for receiving the modulated ramp reference signal and a first output, said first comparator being responsive to said first input signal and said modulated ramp reference signal and operative to produce a first output signal on said first output which changes state when the voltage level of the modulated ramp reference signal exceeds the voltage level of said first input signal;
a second comparator having a third input connected to said second terminal for receiving said second input signal, a fourth input for receiving the modulated ramp reference signal and a second output, said second comparator being responsive to said second input signal and said modulated ramp reference signal and operative to produce a second output signal on said second output which changes state when the voltage level of the modulated ramp reference signal exceeds the voltage level of said second input signal; and
a logic circuit coupled to said first and second outputs, said logic circuit being responsive to said first and second output signals and operative to produce a pulse having a duration that corresponds to the time difference between the changes of state of said first output signal and said second output signal, such duration being indicative of the voltage difference between said first input signal and said second input signal.
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Abstract
An analog-to-digital converter of the single slope detection type comprising a first input terminal for receiving a first input signal formed by the superposition of a common mode noise voltage on a first DC voltage, a second input terminal for receiving a second input signal formed by the superposition of the common mode noise voltage on a second DC voltage, a ramp generator responsive to the second input signal and operative to separate the common mode noise voltage from the second input signal and to develop a ramp reference signal that is modulated by the common mode noise voltage, a first comparator for comparing the signals at the first terminal and at the output of the ramp generator and for developing a first output signal which changes state when the level of the modulated ramp reference signal exceeds the level of the first input signal, a second comparator for comparing the signals at the second terminal and at the output of the ramp generator and for developing a second output signal which changes state when the level of the modulated ramp reference signal exceeds the level of the second input signal, and a logic circuit responsive to the first and second output signals and operative to produce a pulse having a duration that corresponds to the time difference between the changes of state of the first and second output signals and operative to produce a pulse having a duration that corresponds to the time difference between the changes of state of the first and second output signals, such duration being indicative of the voltage difference between the first input signal and the second input signal. CROSS-REFERENCE TO RELATED APPLICATION
This application is a continuation-in-part of application Ser. No. 627,718, filed Oct. 31, 1975, now abandoned.
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Citations
10 Claims
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1. An analalog-to-digital converter of the single slope detection type comprising:
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a first input terminal for receiving a first input signal formed by the superposition of a common mode noise voltage on a first DC voltage; a second input terminal for receiving a second input signal formed by the superposition of said common mode noise voltage on a second DC voltage; ramp generating means coupled to said second input terminal and receiving said second input signal;
said ramp generating means operative to isolate said common mode noise voltage from said second input signal and to develop a ramp reference signal that is modulated by said common mode noise voltage;a first comparator having a first input connected to said first terminal for receiving said first input signal, a second input for receiving the modulated ramp reference signal and a first output, said first comparator being responsive to said first input signal and said modulated ramp reference signal and operative to produce a first output signal on said first output which changes state when the voltage level of the modulated ramp reference signal exceeds the voltage level of said first input signal; a second comparator having a third input connected to said second terminal for receiving said second input signal, a fourth input for receiving the modulated ramp reference signal and a second output, said second comparator being responsive to said second input signal and said modulated ramp reference signal and operative to produce a second output signal on said second output which changes state when the voltage level of the modulated ramp reference signal exceeds the voltage level of said second input signal; and a logic circuit coupled to said first and second outputs, said logic circuit being responsive to said first and second output signals and operative to produce a pulse having a duration that corresponds to the time difference between the changes of state of said first output signal and said second output signal, such duration being indicative of the voltage difference between said first input signal and said second input signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification