Pattern recognition system

• US 4,021,778 A
• Filed: 08/02/1976
• Issued: 05/03/1977
• Est. Priority Date: 08/01/1975
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ueda, Hirotada, Uno, Takeshi, Ikeda, Sadahiro
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US05/710,417
• Time in Patent Office: 274 Days
• Field of Search: 340/146.3 M, 340/146.3 MA, 340/146.3 AC, 340/146.3 Q, 340/146.1 AB, 340/146.1 AL, 340/146.1 AQ, 340/146.1 AV , 340/146.1 BA, 235/177, 235/182, 235/186, 235/189, 307/216
• US Class Current: 382/203
• CPC Class Codes: G06V 10/443 by matching or filtering

Abstract

A pattern recognition system comprises a partial pattern cutting out system which has a plurality of cutting out windows previously provided in correspondence with a plurality of regions in a specific pattern which respectively correspond to a characteristic part of the specific pattern to be recognized and which constitute patterns symmetric to each other. A binary input signal is cut out by the use of the partial pattern cutting out apparatus. The "EXCLUSIVE OR" function between the corresponding bits of the partial patterns obtained from the plurality of cutting out windows are evaluated by "EXCLUSIVE OR" circuits. The number of outputs of predetermined logic level among the outputs of the "EXCLUSIVE OR" circuits and a preset number are compared, and the coincidence between both the numbers is sought. When both numbers coincide, the inputted signal is recognized as being the specific pattern.

Claims

1. A pattern recognition system for recognizing a specific pattern having at least first and second symmetrical portions from a binary representation of a subject pattern, comprising

first means for detecting those portions of binary signal representing the subject pattern which are located at the positions of said first and second symmetrical portions in the pattern to be recognized.

second means responsive to said first means for effecting an EXCLUSIVE OR operation between said detected pattern portions, and

third means responsive to the output of said second means for indicating whether the signal obtained from said second means designated recognition of said specific pattern.

2. A pattern recognition system according to claim 1 wherein said first means comprises memory means for storing said binary signal and detection means for detecting the binary data stored in those portions of said memory means at which the data relating to said first and second symmetrical pattern portions are stored.

3. A pattern recognition system according to claim 2 wherein said second means comprises a plurality of EXCLUSIVE OR gates each receiving input signals made up of a corresponding bit from each of said portions of said memory means storing said first and second symmetrical pattern portions.

4. A pattern recognition system according to claim 3 wherein said third means comprises addition means for adding the output signals of said second means, and comparison means connected to said addition means for comparing the value of the output signal of said addition means and a reference value determined from said specific pattern.

5. A pattern recognition system according to claim 3 wherein said third means comprises an AND circuit for performing an AND logic operation on the output signals of said second means.

6. A pattern recognition system according to claim 1, further comprising fourth means coupled to said third means for distinguishing first and second types of patterns corresponding to characteristic parts of said specific pattern, said first and second types of patterns being identified by said third means and being converse to each other.

7. A pattern recognition system according to claim 6, wherein said fourth means comprises an "AND" circuit and an "INHIBIT" circuit connected to perform "AND" and "INHIBIT" logic operations, respectively, between signals corresponding to a third partial pattern cut out from said first means and signals obtained from said third means.

8. A pattern recognition system according to claim 6, further comprising fifth means connected to said fourth means for calculating the distance between said first and second types of patterns corresponding to the characteristic parts of said specific pattern from coordinates ot the partial patterns at the time when an output signal is obtained from said fourth means and for judging if the calculated value is equal to the corresponding distance of said specific pattern.

9. A pattern recognition system according to claim 8, wherein said fifth means comprises first and second gate means for gating signals representative of coordinates of the partial patterns cut out with two output signals of said fourth means, first and second memory means for storing output signals of said first and second gate means, subtraction means for evaluating the difference between the signals representative of the coordinates stored in said first and second memory means, and comparison means for comparing the value of the output signal of said subtraction means and a reference value evaluated from said specific pattern.

10. A pattern recognition system according to claim 1 wherein said third means comprises addition means for adding the output signals of said second means, and comparison means connected to said addition means for comparing the value of the output signal of said addition means and a reference value determined from said specific pattern.

11. A pattern recognition system according to claim 1 wherein said third means comprises an AND circuit for performing an AND logic operation on the output signals of said second means.