Clock synchronization system

• US 4,021,784 A
• Filed: 03/12/1976
• Issued: 05/03/1977
• Est. Priority Date: 03/12/1976
• Status: Expired due to Term

• Current Assignee: Sperry Rand Corporation (Unisys Corporation)
• Original Assignee: Sperry Rand Corporation (Unisys Corporation)
• Inventors: Kimlinger, Joseph Anthony
• Primary Examiner(s): Nusbaum, Mark E.
• Application Number:
  US05/666,279
• Time in Patent Office: 417 Days
• Field of Search: 340/172.5, 445/1, 178/69.5
• US Class Current: 713/401
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

In a fail soft synchronization clock system having a plurality of central processing units and a plurality of input-output units operably connected to one or more remotely located volatile cache memories there is provided a free-running, non-synchronized clock in each central processing unit. The clock outputs are connected to sets of synchronizing clock system logic circuits, one for each central processing unit, which disable the clocks of all other central processing units and selects their own associated clock as the input for producing a plurality of synchronized outputs employed in turn to time the operation of the processing system which is operably connected to the cache memories.

Claims

1. A fail soft synchronization clock system for a plurality of central processing units operably connected to remotely located volatile cache memory means, comprising:

a plurality of central processing units,

a clock in each central processing unit adapted to generate non-synchronized clock pulses of the same time duration,

a plurality of input-output units,

volatile cache memory means connected to said input-output units and to said central processing units for receiving generated requests from said units for the input or output of data in said memory,

synchronizing clock system logic means having inputs connected to the outputs of said clocks,

said synchronizing clock system logic means comprising control gating means for determining which central processing unit clock shall be connected to said central processing units, said input-output units and to said volatile cache memory means and for connecting the selected central processing unit clock to said units and said memory means,

said synchronizing clock system logic means further including means for generating a plurality of timed outputs synchronized one with the other,

each of said plurality of timed outputs being connected by individual lines to one of said input-output units, said central processing units and to said volatile cache memory means, and

adjustable delay means in each of said individual lines for producing non-synchronized clock pulses, whereby said input-output units and said central processing units generate requests for the input or output of data immediately prior to the volatile cache memory means being enabled by the non-synchronized clock pulses to accept a request for the input or output of data.

2. A fail soft synchronization clock system as set forth in claim 1,

wherein said synchronizing clock logic means synchronized outputs are timed by the central processing unit clock selected to be operably connected to said central processing units, said input-output units and to said volatile cache memory means, and which further includes,

adjustable delay means connected between the input of the synchronizing clock system logic means and to the selected clock.

3. A fail soft synchronization clock system as set forth in claim 2 wherein said synchronizing clock logic means further comprises a set of logic circuits for each central processing unit for selecting the clock associated with its own central processing units, said set of logic circuits further having its own non-synchronized clock inputs and including means for generating synchronized outputs, and delay means for producing non-synchronized clock pulses from said synchronized outputs.

4. A fail soft synchronization clock system as set forth in claim 3 which further includes a transactional logic unit for comparing the decision made at each set of logic circuits and for overriding an incorrect decision made by said logic circuits.

5. A fail soft synchronization clock system as set forth in claim 1 wherein said synchronizing clock system logic further includes,

means for switching from one clock to another during continuing operation of one or more central processing units.

6. A fail soft synchronization clock system as set forth in claim 5 wherein said means for switching from one clock to another comprises gating circuits for blocking the outputs from said synchronizing clock system logic means for a predetermined number of clock pulses.

7. A fail soft synchronization clock system as set forth in claim 1 wherein said synchronized outputs from said synchronizing clock system logic means further include an enabling clock pulse for each input-output unit, each said enabling clock pulse having an active request portion occurring in time apart from the other active request portions.

8. A fail soft synchronization clock system as set forth in claim 7 wherein said synchronizing clock system logic means further includes means for generating an internal switching clock pulse having an active switching time for selectively disabling all of said outputs from said logic for one or more basic cycle times.

9. A fail soft synchronization clock system as set forth in claim 8 wherein said internal switching clock pulse occurs after said active request portion of said input-output enabling clock pulses and before the end of basic cycle time,

and further including internal logic gating means for enabling said outputs from said logic means during a subsequent basic cycle time and during said active switching time.

10. A fail soft synchronization clock system as set forth in claim 8 which further includes means for generating a guard pulse beginning before, and ending before, the start of said active switching time of said internal switching clock pulse,

said guard pulse being connected to the clock of the central processing unit which is connected to said synchronizing clock system logic means,

and means for generating an enabling pulse after terminating said guard pulse and during said active switching time pulse for informing the non-resident clock.