Interface system for coupling an indeterminate number of peripheral devices to a central processing unit

• US 4,024,505 A
• Filed: 11/18/1974
• Issued: 05/17/1977
• Est. Priority Date: 11/18/1974
• Status: Expired due to Term

• Current Assignee: Lloyds Bank Limited (Lloyds Banking Group PLC)
• Original Assignee: CompuCorp
• Inventors: Sperling, Irving
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/524,802
• Time in Patent Office: 911 Days
• Field of Search: 340/172.5, 340/147, 340/146.1 BA, 360/48, 360/49, 360/50, 360/53, 179/15 AL, 235/153 A, 235/153 AP
• US Class Current: 710/2
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence

Abstract

A system is provided for coupling an indeterminate number of peripheral devices to a central processing unit (CPU) through a single receptacle. A cable connected to an interface unit (IU) of a first device plugs into the CPU receptacle. Cables of subsequent IUs are plugged into receptacles connected to earlier plugged IUs, thus connecting the cables of all devices in series and the device IU'"'"'s themselves in parallel. One type of IU is for a magnetic tape cassette and includes a timeout circuit to determine when certain types of programming errors have occurred. A binary digit is set in a status register for that and other types of errors. The status register is read under program control of the CPU, thus providing for the flexibility of haulting operation or bypassing the program section having an error for unattended operation of the CPU.

Claims

1. A data processing system comprising a central processing unit having a receptacle through which an interface unit of a peripheral device is connected by an associated cable, said interface unit having a receptacle to which another interface unit may be connected by its own associated cable such that separate cables associated with separate interface units are connected in series, and the interface units are connected in parallel to the central processing unit through the series connected cables, each interface unit being connected to a particular device having its own function of inputting and outputting data words to and from said central processing unit, each interface unit being assigned a unique address code, particular mode-control codes and particular function control codes, and each interface unit having a single input register to receive output words from said central processing unit through said series connected cables, each of said output words being comprised of a predetermined number of binary digits representing either an address code and a mode-control code combined, a function control code or data, means connected to said input register for decoding an address code and a mode control code to select a particular device for a particular mode of operation, means connected to said input register for decoding a function code for controlling a particular function of said particular device within said particular mode, and means responsive to mode control signals transmitted by said central processing unit over said series-connected cables for controlling the utilization of output words stored in said input register as an address code and mode-control code combined, a function control code or data, each interface unit further having gating means for transmission of input data words to said central processing unit through said series-connected cables, each of said input data words being comprised of a predetermined number of binary digits, said gating means being connected to be responsive to said mode-control decoding means.

2. A data processing system as defined by claim 1 wherein each interface unit includes a status register and means for storing binary digits in said register independent of said central processing unit, each of said binary digits including the status of some particular aspect of the particular device serviced by the interface unit, means for connecting said status register to said gating means for the purpose of inputting to said central processing unit through said series connected cables the content of said status register under control of said gating means by a particular mode-control code.

3. A data processing system as defined by claim 2 wherein at least one of said interface units includes keyboard means for manual inputting of binary coded signals to said central processing unit, a keyboard register for storing binary coded signals from said keyboard means, means for connecting said keyboard register to said gating means for the purpose of inputting to said central processing unit through said series connected cables the content of said keyboard register under control of said gating means by a particular mode-control code operating said gating means.

4. A data processing system as defined by claim 3 wherein a plurality of interface units include a keyboard means, and wherein each keyboard register includes means for entering as part of the binary coded signal inputted to said central processing unit a code uniquely identifying the interface unit and means for entering a binary digit in a predetermined position of said status register indicative of the fact that said keyboard means has been actuated for manual inputting of binary coded signals.

5. A data processing system as defined by claim 4 wherein each interface unit includes means for setting and transmitting to said central processing unit a signal through said series connected cables indicating that a keyboard entry has been made into said keyboard register and that a binary digit has been entered in said predetermined position of said status register.

6. A data processing system as defined in claim 5 including means responsive to said address decoding means and said mode control decoding means for resetting said signal that indicates a keyboard entry has been made into said keyboard register, thus terminating transmission of said signal to said central processing unit when said central processing unit responds to said signal with an appropriate address code and mode control code in an output word.

7. A data processing system as defined in claim 2 wherein at least one of said peripheral devices is a magnetic tape cassette and the interface unit servicing said cassette includes means for detecting gaps between records, each record comprising a block of data, timeout means operative when said cassette interface unit is active in controlling the cassette for initiating an error in the condition when a predetermined time measured by said timeout means expires, and means for resetting said timeout means in response to each inter-record gap detected by a said gap detecting means, thus initiating an error indication if an inter-record gap is not detected within a maximum time.

8. A data processing system as defined in claim 7 wherein said error indicating means comprises means for setting a binary digit in said status register, thus permitting a stored program in said central processing unit to test for an error and take appropriate action.

9. A system for coupling an indeterminate number of peripheral devices to a central processing unit through a single receptacle for direct synchronous communications between said unit and any selected one of said devices in response to programmed instructions, said system comprising an interface unit for each device, each device interface unit having a cable adapted to be plugged into a receptacle through which signals are transmitted to and from said central processing unit, and having a receptacle into which a cable of another device interface unit may be plugged in, thus connecting cables of all device interface units in series and the device interface units in parallel, each interface unit being organized in the same way for two-way communication over separate series-connected lines in said series-connected cables for communication in each direction, and having a single control register connected to said cable to receive both data and control code groups of binary digits under control of mode control signals from said central processing unit transmitted through separate lines over said cable means for decoding an address code in a received control code group of binary digits by comparison with a fixed code assigned to the interface unit and its connected peripheral device, means responsive to both said address decoding means and said mode control signals for controlling the utilization of groups of binary digits as data and control codes, and for storing and decoding a control code group of binary digits subsequent to a control code group having said address code when said mode control signals are in a control transfer mode, but only by the addressed interface, said storing and decoding means providing static decoded control signals until said mode control signals are again in the control transfer mode to address an interface unit, and means for transmitting synchronizing clock pulses to all interface units in parallel by said central processing unit through said series-connected cables.

10. A system as defined in claim 9 wherein a group of binary digits is transmitted from a selected one of a plurality of registers in an addressed peripheral device interface unit to said central processing unit in response to said control code storing and decoding means while said mode control signals are in a data transfer mode immediately following a control transfer mode.

11. A system as defined in claim 10 wherein one of said plurality of registers is a status register storing a group of binary digits indicative of the status of said addressed peripheral device interface unit.

12. A system as defined in claim 11 wherein each interface unit includes keyboard means for manual inputting of binary coded signals, and one of said plurality of registers is a keyboard buffer register storing a group of binary digits manually inputted through said keyboard means and including means for setting a predetermined binary digit in said status register in response to any keyboard entry, and means for transmitting a signal to said central processing unit indicative of the fact a keyboard entry has been made, whereby a program stored in said central processing unit may read the status register of each interface unit to determine which has a keyboard entry stored in a keyboard register.

13. A data processing system as defined in claim 12 including means responsive to said address decoding means and said control-code storing and decoding means when said mode control signals are in a control transfer mode for terminating transmission of said signal to said central data processing unit indicating a keyboard entry has been made when said central processing unit responds to said signal with an appropriate address code and control code transmitted to said control register.

14. A system as defined in claim 11 including in each interface unit a function register connected to said control register for storing a function code transmitted to said control register in response to said control code storing and decoding means enabled by said address decoding means when said mode control signals are in a data transfer mode following a control transfer mode during which an address and control code was transmitted to said control register, thereby placing only an addressed interface unit into a function mode for operation of said peripheral device in accordance with the function code.

15. A system as defined in claim 14 including means in at least one interface unit of slow peripheral device for generating an interrupt signal and transmitting said interrupt signal to said central processing unit through said series connected cables whenever said peripheral device operating under control of said function code in said function register requires a data group of digits to be transmitted between said peripheral device and said central processing unit, and means for storing a binary digit in a unique location of said status register indicating that an interrupt signal has been generated, whereby said central processing unit may, under its programmed control, read out the contents of said status registers in peripheral device interface units in sequence to determine which has generated an interrupt signal in order that the interface unit which has done so be serviced.

16. A data processing system as defined in claim 12 including means responsive to said address decoding means and said control code storing and decoding means when said mode control signals are in a control transfer mode for terminating transmission of said interrupt signal when said central processing unit responds to said signal with an appropriate address code and control code transmitted to said control register.

17. A system as defined in claim 16 including bistable means in each peripheral device interface unit having an interrupt signal generating means for inhibiting a signal generated by said interrupt generating means from being transmitted over said series-connected cables, said bistable means being set by a control code stored and decoded by said storing and decoding means in each peripheral device interface unit at the end of a control transfer mode in order to inhibit interrupts under programmed control, said bistable means being reset by another control code stored and decoded by said storing and decoding means in each peripheral device interface unit at the end of a control transfer mode to restore interrupts under programmed control.

18. A system as defined in claim 11 wherein one of said interface units is for control of a magnetic tape unit for storage and reading of blocks of data, said blocks of data being separated by blank interrecord gaps, said one interface unit including means for detecting interrecord gaps, means for timing out a predetermined period greater than a maximum time required to drive tape past a read station from one interrecord gap to another, means for resetting said timeout means in response to each interrecord gap detected, and means for entering an error indicating binary digit in said status register, whereby a program in said central processing unit may test for an error in the immediately preceding input-output operation by transferring the contents of said status register to said central processing unit for inspection of said error indicating binary digit.

19. A system as defined in claim 18 wherein said magnetic tape unit employs a cassette for reel to reel winding with clear leader at each end, and wherein said timeout means includes means operative for inhibiting it from timing out while only writing and while erasing tape, and while winding tape either forward or backward, except while on said leader where lack of interrecord gaps will cause timeout for any operation of said magnetic tape unit.

20. A data processing system in which a central processing unit transfers blocks of data to a magnetic tape and recieves blocks of data from said magnetic tape through an interface unit under programmed instruction control of said central processing unit, said blocks of data stored on said magnetic tape being separated by blank inter-record gaps, said interface unit including a status register and, means for detecting inter-record gaps, time-out means for timing out a predetermined period greater than a maximum time required to drive said magnetic tape past a read station from one interrecord gap to another, means for resetting said timeout means in response to each interrecord gap detected, and means for entering an error indicating binary digit in said status register, whereby a program in said central processing unit may test for an error in the immediately preceding input-output operation by transferring the contents of said status register to said central processing unit for inspection of said error indicating binary digit.

21. A system as defined in claim 20 wherein said magnetic tape is housed in a cassette for reel to reel winding with clear leader at each end, and wherein said timeout means includes means operative for inhibiting it from timing out while only writing and while erasing tape, and while winding tape either forward or backward, except while on said leader where lack of interrecord gaps will cause timeout for any operation of said interface unit.

22. A data processing system in which a central processing unit transfers blocks of data to and receives blocks of data from magnetic tape through an interface unit under control of a programmed instruction in said central processing unit, said blocks of data being stored on said magnetic tape in succession, each with a header including an identification number used by said central processing unit for verification of data being addressed by said programmed instruction, each block of data being numbered in sequence from one end of said tape to the other in order for said central processing unit to keep track of magnetic tape position by counting up and down data blocks as tape is driven forward and backward in order to provide a tape position number for comparison with a block position number written as part of said identification number for verification when the block of data which follows on said magnetic tape is again accessed by said central processing unit, said header including a preamble of a predetermined binary code and said interface unit including means for detecting the first ones in sequence of less than the total number of binary digits in said code before commencing to record in response to an instruction from said central processing unit to rewrite a block of data over a recorded block, and means for automatically recording the balance of said preamble in synchronism, followed by said identification number and block of data whereby rewriting a block of data is synchronized by resynchronizing said preamble without requiring separate timing.