Correlator device

• US 4,025,775 A
• Filed: 06/04/1976
• Issued: 05/24/1977
• Est. Priority Date: 06/10/1975
• Status: Expired due to Term

• Current Assignee: Thomson-CSF
• Original Assignee: Thomson-CSF
• Inventors: Carre, Roland, Beauvais, Thierry
• Primary Examiner(s): Gruber, Felix D.
• Application Number:
  US05/692,872
• Time in Patent Office: 354 Days
• Field of Search: 235/181, 235/150.53, 328/133, 328/134, 307/232, 343/17.2 R, 343/17.5, 343/7.7, 329/50, 329/112, 329/122, 325/60
• US Class Current: 708/5
• CPC Class Codes: G06F 17/15 Correlation function computation including computation of convolution operations arithmetic circuits for sum of products per se, e.g. multiply-accumulators G06F7/5443; digital filters, e.g. FIR, IIR, adaptive filters H03H17/00
• CPC Class Codes: G06G 7/1928 for forming correlation integrals; for forming convolution integrals G06G7/195, G06G7/1907 and G06G7/1914 take precedence

Abstract

The present invention relates to devices for correlating two phase-modulated signals, in order to determine the delay between said two signals. The signals are applied to phase detectors which receive one and the same local wave. One of the signals is delayed by a variable delay time. The phase values obtained are subtracted from one another. The result is then integrated in the complex plane for a given period of time. The variation of the variable delay permits to determine the correlation function and in particular, the position and the amplitude of the correlation peak.

Claims

1. A correlator device for determining the correlation function of two phase-modulated signals having a given carrier frequency comprising, phase detecting means to which the said modulated signals are applied separately for delivering the phase difference φ

1 and φ

2 between said modulated signals and a reference signal, delay means for delaying one of the signals in relation to the other by a variable delay time, subtractor means for forming the difference φ

1- φ

2, computing means for forming the sine and the cosine of the difference φ

1- φ

2, for integrating separately said sine and cosine during a given period of time and, for delivering the sum of the square of the result of said integrations, and means for varying said variable delay time.

2. A correlator device for determining the correlation function of two phase-modulated signals having a given carrier frequency comprising, phase detecting means to which the said modulated signals are applied separately for delivering the phase differences φ

1 and φ

2 between said modulated signals and a reference signal, sampling and storing means for storing separately series of samples of said phase differences φ

1 and φ

2, read-out means for reading out the two series of stored samples in accordance with the chronological order of recording and with a variable shift between the samples of one series in relation to those of the other, subtractor means for forming the phase difference φ

1- φ

2 of each pair of samples read-out, computing means for forming the sine and the cosine of said phase difference φ

1- φ

2, for integrating separately said sine and cosine during the read out time of the samples and for delivering the sum of the square of the results of integrations, and means for varying said variable shift.

3. A correlator device as claimed in claim 2, further comprising interpolating means for computing the value of the correlation function between two successive values delivered by the computing means.

4. A correlator device as claimed in claim 3, further comprising means for evaluating the difference in time between the peak of the correlation function and a reference instant, said difference in time being equal to the delay time between the input signals.

5. A correlator device as claimed in claim 2, wherein said sampling and storing means comprises a store for storing each series of phase samples, an address circuit connected to said store for addressing each sample in a given part of said store, a pair of switching means for sampling each phase difference, arranged respectively up-circuit and down-circuit of said phase detecting means and control circuit means for controlling sequentially the pairs of switching means.

6. A correlator device as claimed in claim 5, wherein said phase detecting means comprises an oscillator for delivering a reference signal having a frequency substantially equal to the carrier frequency of the input signals, a phase detector for receiving sequentially said input signals and said reference signal and coding means connected to said detector for delivering the phase difference between said signals.

7. A correlator device as claimed in claim 5, wherein each store comprises at least two sub-stores and swtiching means arranged up-circuit and down-circuit thereof, so that one of the two substores operates in the recording mode whilst the other is performing read out, and vice-versa.

8. A correlator device as claimed in claim 3, wherein said interpolation means comprise a first store supplied with the successive output signals of the computing means, a second store containing samples of a predetermined weighting function, multiplying means for multiplying a given number of output signals stored in the first store by the same number of samples stored in the second store, and means for adding the successive results of said multiplying means.

9. A correlator device as claimed in claim 8, further comprising a threshold comparator for receiving the output signal of the adding means and a threshold signal, a counter circuit advanced in synchronism with the computation of each output signal of the adding means, a first buffer store connected to said counter and controlled by said threshold comparator for storing the value in the counter when the said output signal exceeds the threshold signal, a second buffer store connected to said counter and controlled by said threshold comparator for storing the value in the counter when the said output signal undershoots said threshold signal, arithmetic mean computing means connected to said buffer stores for computing the arithmetic mean of the contents of said stores and multiplying means for multiplying said arithmetic mean by a number which represents the recurrence period of the said output signals.

10. A correlator device as claimed in claim 9, further comprising a subtractor circuit connected to said buffer stores for delivering an indication of the width of the correlation peak.

11. A correlator device as claimed in claim 9, further comprising comparator means for comparing the values of two successive output signals of the computing means, and switching means connected between the output of said computing means and an output terminal for delivering the value of the correlation peak amplitude, said switching means being controlled by said comparator means in order to transmit the peak value to the output terminal when the compared values are equal.

12. A correlator device as claimed in claim 11, further comprising a multiplying circuit connected to said output terminal, for furnishing to the threshold comparator a threshold signal which is proportional to the peak amplitude.