Multi-level clipping circuit

• US 4,025,803 A
• Filed: 03/01/1976
• Issued: 05/24/1977
• Est. Priority Date: 03/01/1976
• Status: Expired due to Term

• Current Assignee: Control Data Corporation (Ceridian HCM Holding, Inc.)
• Original Assignee: Control Data Corporation (Ceridian HCM Holding, Inc.)
• Inventors: Norberg, Gayle Russell
• Primary Examiner(s): Miller, Jr., Stanley D.
• Application Number:
  US05/662,314
• Time in Patent Office: 449 Days
• Field of Search: 307/237, 307/318, 307/304, 328/171, 328/172, 328/168, 328/169, 328/62, 328/31, 328/32, 328/54, 324/77 A, 323/9
• US Class Current: 327/86
• CPC Class Codes: G01R 19/17 giving an indication of the number of times this occurs , i.e. multi-channel analysers

Abstract

A circuit receiving a varying waveform and providing a plurality of signals, each signal changing when the waveform crosses a predetermined voltage level associated with that signal.

Claims

1. A circuit for providing first through nth, n at least 2, output signals, each changing responsive to the crossing of an associated predetermined voltage level by a varying input signal appearing across first and second input signal terminals, the first at times more positive than the second and comprising:

(a) first through nth breakdown devices each having a preselected voltage drop from a first to a second terminal;

(b) a zeroeth connector connecting one terminal of the first breakdown device to the input signal terminal having the same ordinal designation;

(c) first through n-1th connectors connecting the first through nth devices in a series string in ascending ordinal designation, each of the first through n-1th connectors respectively connecting terminals of opposite ordinal designation on devices having the same and one greater ordinal designations, and the first connector connected to the first device'"'"'s terminal which is not connected to the signal terminal; and

(d) first through nth return path resistors, all having a first terminal connected to the input signal terminal which is not connected to the first breakdown device, the first through n-1th having their second terminal connected respectively to the first through n-1th connectors, and the nth having its second terminal connected to that terminal of the nth breakdown device which is not connected to the n-1th connector;

wherein the preselected breakdown device voltage drops are selected such that the sum of the voltage drops between the zeroeth and ith connectors substantially equals the predetermined voltage level associated with the ith output signal, and wherein the first through nth output signals appear respectively across the first through nth return path resistors.

2. The circuit of claim 1, wherein the breakdown devices are four-layer diodes.

3. The circuit of claim 1, wherein the breakdown devices are gas tubes.

4. The circuit of claim 1, wherein the breakdown devices are zener diodes.

5. The circuit of claim 4, further comprising a cutoff diode interposed between the first zener diode and the zeroeth connector, and oriented to be forward biased by the current flow through the zeroeth connector when the first input signal terminal is more positive than the second.

6. The circuit of claim 5, wherein the first input terminal is always more positive than the second, and the zeroeth connector is connected to the first input signal terminal.

7. The circuit of claim 5, wherein the second input terminal is always more positive than the first, and the zeroeth connector is connected to the second input signal terminal.

8. The circuit of claim 5, including a rectifier receiving an AC signal, and supplying the rectified AC signal to the input signal terminals.

9. The circuit of claim 8, wherein the rectifier comprises a transformer coupled full-wave rectifier.

10. The circuit of claim 9, further comprising first through nth amplifiers having similar response times and, supplying the first through nth output signals respectively, with the inputs of each connected across the return path resistor having that amplifier'"'"'s ordinal designation.

11. The circuit of claim 10, wherein each amplifier comprises an insulated gate field effect transistor receiving the output signal.

12. The circuit of claim 11, wherein the rectifier comprises

(a) transformer having a primary winding receiving the input signal and a secondary winding having twice the total turns of the primary, first and second end taps, and a center tap supplying the input signal to the cutoff diode;

and

(b) first and second rectifier diodes each having the electrode matching the zener diodes'"'"' second electrode connected to the first and second end taps, respectively of the secondary, and the other terminal of each to the second terminals of the return path resistors.

13. The circuit of claim 12 wherein the cutoff diode connects the secondary center tap to the first zener diode, electrodes of the cutoff diode and the zener diode connected to each other matching.

14. The circuit of claim 1, further comprising a cutoff diode interposed between the first breakdown device and the zeroeth connector, and oriented to be forward biased by current flow through the zeroeth conductor when the first input signal terminal is more positive than the second.

15. The circuit of claim 14, further comprising a full-wave rectifier receiving an AC signal and supplying the rectified AC signal to the input signal terminals.

16. The circuit of claim 15, further comprising first through nth similar high input impedance amplifiers supplying the first through nth output signals respectively, with the inputs of each connected across the return path resistor with that amplifier'"'"'s ordinal designation.