Automatic modular memory address allocation system

• US 4,025,903 A
• Filed: 09/10/1973
• Issued: 05/24/1977
• Est. Priority Date: 09/10/1973
• Status: Expired due to Term

• Current Assignee: Computer Automation Incorporated
• Original Assignee: Computer Automation Incorporated
• Inventors: Henry, George C., Kaufman, Phillip A., Blacksher, Roy, Gorman, Kenneth C.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Rhoads, Jan E.
• Application Number:
  US05/395,548
• Time in Patent Office: 1,352 Days
• Field of Search: 340/172.5, 444/1, 445/1
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0676 the address being position dependent

Abstract

A modular minicomputer is provided which is assembled from a central processor unit module and a plurality of memory modules. Small calculators on the memory modules are so interlocked that when the computer is powered up, memory address boundaries are calculated automatically. As a result, the bank of memory modules appears to the central processing unit the same as a single large memory unit.

Claims

1. In a digital computer having a processing unit and a system for selectively addressing individual memory cells of a memory bank having a series of separate memory units, each said memory unit containing a number of such memory cells, for storing information in or for reading out information from each cell in accordance with a corresponding selectable absolute address signal generated by said processing unit to represent the absolute address thereof corresponding to said each cell, the combination of:

a plurality of signal sources for providing signals representative of the number of memory cells in the respective memory units, said signal sources being associated with said memory units on a one-to-one basis;

starting address means for establishing a fixed starting address for the first memory unit in the series and for generating a signal representing said starting address;

a plurality of calculating means associated with said memory units on a one-to-one basis, each such calculating means being controlled by the signal source of the associated memory unit and in accordance with a starting address signal of the associated memory unit for establishing a unique ending address for said associated memory unit, and for generating a signal representing said unique ending address, each such calculating means but the last also being controlled by the signal source of the corresponding memory unit and in accordance with the starting address signal of the associated memory unit for establishing a starting address for the next memory unit in the series, whereby a local address range is established for each said memory unit, and the absolute address is established for each cell in each said memory unit; and

a plurality of range detectors associated with said memory units on a one-to-one basis, each such range detector being responsive to a signal generated by said processing unit to represent a selected absolute address and also responsive to the starting and ending address signals of the associated memory unit, for enabling said memory unit to select a memory cell corresponding to said selected address only when said selected absolute address lies within the local address range of said memory unit.

2. In a digital computer having a processing unit and a system for selectively addressing individual memory cells of a memory bank having a series of separate memory units, each said memory unit containing a number of such memory cells, for storing information in or for reading out information from each cell in accordance with a corresponding selectable absolute address signal generated by said processing unit to represent an absolute address, the combination of:

a corresponding series of memory capacity signal sources associated on a one-to-one basis with the respective memory units for supplying a digital signal representing the memory cell capacity of each respective memory unit;

starting address means for establishing an initial fixed starting address for the first memory unit in the series,

means associated with each said memory unit for storing a starting address and for generating a signal representing said starting address;

means controlled by the signal source associated with each memory unit that is followed by another unit and controlled by the starting address signal for said each memory unit for establishing a unique ending address for said each memory unit and a unique starting address for the next following memory unit in the series in accordance with said starting address signal of said memory unit and the memory capacity of said each memory unit, for generating signals representing said unique starting and ending addresses whereby a local address range is established for each said memory unit and the absolute address is established for each cell in the respective memory units;

and a plurality of range detectors associated with said memory units on a one-to-one basis, each such range detector being controlled in accordance with a selected absolute address signal and in accordance with the starting and ending address signals of the memory unit with which it is associated, for enabling said each memory unit to select a memory cell corresponding to said selected address only when said selected absolute address lies within the local range of said each memory unit.

3. In a digital computer as set forth in claim 2 wherein the ending address of each said memory unit but the last is 1 less than the starting address of the next following memory unit in the series.

4. In a digital computer as set forth in claim 3, an auxiliary memory unit having a number of memory cells, said starting address means establishing an ending address for said auxiliary memory unit 1 less than the memory capacity thereof;

and

an auxiliary range detector controlled in accordance with said selected absolute address signal for enabling said auxiliary memory unit only when the selected absolute address is less than said initial starting address.

5. In a digital computer as set forth in claim 3, means for establishing an upper boundary address 1 greater than the ending address of the last memory unit in the series and for generating a signal representing said upper boundary address;

comparator means controlled in accordance with said upper boundary address signal for detecting whether the absolute address lies above the ending address of said last memory unit, and

means for inhibiting the selection of any of said memory cells if the absolute address lies above said last mentioned ending address.

6. In a digital computer as set forth in claim 3, means for establishing an upper boundary address 1 greater than the ending address of the last memory unit in the series and for generating a signal representing said upper boundary address;

comparator means controlled in accordance with said upper boundary address signal for detecting whether the absolute address lies above the ending address of said last memory unit, and

means for enabling selection of a memory cell only if the absolute address lies below said upper boundary address.

7. In a digital computer having a processing unit and a system for selectively addressing individual memory cells for a memory bank having a plurality of separate memory units, each said memory unit containing a number of memory cells, for storing information in or for reading information from such cells in accordance with a corresponding selectable absolute address signal generated by said processing unit to represent an absolute address, the combination of:

a plurality of memory capacity signal sources associated with said memory units on a one-to-one basis, each signal source supplying a signal representing the memory cell capacity of the memory unit with respect to which said last mentioned signal source is associated;

an auxiliary signal source for establishing an initial digital starting address;

range setting means controlled by said plurality of said signal sources for establishing a unique fixed digital starting address for each individual memory unit

and for establishing a unique fixed ending address for each individual memory unit in accordance with said unique starting address and the memory capacity of said each individual memory unit, and for generating signals representing said starting and ending addresses respectively;

and a plurality of range detectors associated with said memory units on a one-to-one basis, each such range detector being controlled in accordance with a selected absolute address signal and in accordance with the starting and ending address signals of the associated memory unit, for enabling said individual memory unit to select a memory cell therein corresponding to said selected absolute address only when said selected absolute address lies within the local range of the associated memory unit.

8. In a digital computer having a processing unit and a system for selectively addressing individual memory cells of a memory bank having a series of separate memory units, each memory unit of the series containing a number of such memory cells, for storing information in or for reading information out of each cell in accordance with a corresponding selectable absolute address signal generated by the processing unit to represent an absolute address, the combination of:

a corresponding series of memory capacity signal sources, one such signal source within each respective memory unit for supplying a digital signal representing the memory cell capacity of said each respective memory unit;

starting address means for establishing an initial fixed starting address for the first memory unit in the series and for generating a signal representing said initial fixed starting address;

means associated with each said memory unit for storing a starting address signal representing the starting address of said each memory unit;

means controlled by said memory capacity signal source and said initial starting address signal for said first memory unit for establishing a starting address for each remaining memory unit and for establishing an ending address for each memory unit in accordance with said initial starting address signal of said first memory unit and the memory capacities of the prior memory units in the series, and for also establishing a total of the capacities, the range of addresses of each memory unit but the last, extending from said starting address for each memory unit to said ending address for each memory unit, each such ending address being 1 less than the starting address of the next memory unit in the series, and the ending address for one memory unit being 1 less than the aforesaid total,

said controlled means including means for generating signals representing ending addresses respectively for each memory unit, and

a plurality of range detectors associated with said memory units on a one-to-one basis, each such range detector being controlled in accordance with a selected absolute address signal and in accordance with the starting and ending address signals of the memory unit with which it is associated, for enabling said associated memory unit to select a memory cell corresponding to said selected absolute address only when said selected absolute address lies within the local range of said associated memory unit.

9. In a digital computer as set forth in claim 8, an auxiliary memory unit having a number of cells,

said starting address means establishing a fixed ending address for said auxiliary memory unit 1 less than the memory capacity thereof;

and

an auxiliary range detector controlled in accordance with said selected absolute address signal for enabling said auxiliary memory unit only when the selected absolute address is less than said initial starting address.

10. In a digital computer as set forth in claim 9,

means for establishing an upper boundary addres 1 greater than the ending address of the last memory unit in the series and for generating a signal representing said upper boundary address,

comparator means controlled in accordance with said upper boundary address signal for detecting whether the selected absolute address lies above the ending address of said last memory unit, and

means for enabling selection of a memory cell only if the selected absolute address lies below said upper boundary address.

11. In an information processing system including a plural memory system;

and a memory control unit for supplying address signals for addressing corresponding individual memory cells in such memory system for selectively storing information therein or for reading information therefrom in which said memory cells are assigned a series of ordinal symbols to specify their locations, and wherein said plural memory system comprises a series of memory modules,

each memory module comprising

a memory unit having a plurality of said memory cells, the number of memory cells in each memory module being an integral multiple of an integral base number, and

an address range detector corresponding to said module for detecting whether a selected address signal received from such processing system lies within the ordinal range of said module whereby a detected address signal from said processing system actuates a cell in said module only when the cell addressed has an address that lies within the range of said module;

the improvement comprising;

range setting means comprising a capacity signal source in each respective module for generating a signal representing the memory capacity of the memory unit of said each respective module, and

means coupling the address range detectors of successive memory modules in the series and jointly controlled by signals generated in said capacity signal sources for rendering the address range detector corresponding to each memory module responsive only to address signals having addresses within the range of addresses appropriate to each memory module.

12. In an information processing system as defined in claim 11,

a total installed memory system controlled by the range setting means of said memory modules for establishing a total installed memory capacity representing the sum of the ranges of said series of memory modules;

and

memory enabling means responsive to said selected address signal for enabling said memory modules only when said selected address signal represents an address within said total range.

13. In a memory system having installed therein a series of individual memory modules, each memory module having a plurality of individual memory cells,

address generating means for assigning a numerical address to respective memory cells in said memory modules, comprising:

a signal generator for generating an initial fixed starting address signal for establishing a lower boundary address in a first module;

a register in each of said modules for providing a memory capacity signal representing the number of memory cells in the module in which said register is located;

receiving means in each module for receiving and holding a lower boundary address signal for the module in which said receiving means is located;

adder means in each module for combining the lower boundary address signal of that module and the memory capacity signal from the register in that module and holding the sum forming the upper boundary address of that module;

and means for supplying the upper boundary address of each module but the last to the receiving means of the next following module to form the starting address thereof.

14. In a memory system,

memory address boundary calculating and storing means comprising:

lower address boundary receiving means for receiving a digital lower address boundary signal defining the fixed lower boundary address of a group of memory cells in a memory unit;

a local memory capacity register within said memory unit for providing a digital memory capacity signal representing the number of memory cells in said memory unit;

adding means in circuit with said lower boundary receiving means and with said local memory cell register for summing said lower boundary address signal and said memory capacity signal to produce a signal that represents a digital upper address boundary for said module; and

means for receiving a selectable digital absolute address signal that has more digits than said memory capacity signal, said selectable absolute address signal having a range component and a local address component that are partially non-overlapping; and

means controlled by the range component of said absolute address signal and said stored boundary address signals for generating a signal to provide access to memory cells corresponding to the local address component of said absolute address signal only when said absolute address signal lies within a range defined by said boundaries.

15. In a memory system as defined in claim 14,

said lower address boundary receiving means comprising a serial-to-parallel shift register.

16. In a memory system as defined in claim 15, wherein said adder means generates said upper address boundary signal in parallel form,

a parallel-to-serial shift register for converting said upper address signal boundary from parallel to serial form.

17. In a modular memory system for a digital computer,

a series of memory address boundary calculating and storing means associated with a series of ordered memory units on a one-to-one basis, each such means and each such memory unit having an input and an output respectively and each such means comprising:

lower address boundary signal receiving and converting means for receiving a digital signal in serial form, said digital signal defining the fixed lower boundary address of a group of memory cells in the corresponding memory unit and for converting said digital signal to parallel form;

a local memory capacity register for providing a digital memory capacity signal representing the number of memory cells in said corresponding memory unit;

adding means in circuit with said lower boundary signal receiving means and with said local memory capacity register for summing said lower address boundary signal and said memory capacity signal to generate a digital upper address boundary signal for said memory unit; and

means for converting said upper boundary signal from parallel form to serial form and applying it to the output of said boundary calculating and storage means;

means for connecting the output of each but the last of said calculating and storing means to the input of the next in series;

means for supplying an initial starting address signal to the input of the first memory unit in said series of memory units;

means for receiving and storing the upper boundary address signal of the last memory unit in said series,

means in each said memory unit for receiving a selectable digital absolute address signal that has more digits than the memory capacity signals for the respective memory units;

said absolute address signal having a range component and a local address component that are partially non-overlapping; and

means controlled by the range component of said absolute address signal and said stored boundary address signals for generating a signal for enabling a memory unit with the local address component of said absolute address signal only when said absolute address signal lies within a range defined by the boundaries of said last mentioned memory unit.

18. A memory module having a number of memory cells for use in a minicomputer system, comprising:

a signal source on said module for generating a memory capacity signal representative of said number of memory cells;

means for receiving an external boundary defining signal;

range calculating means controlled by said memory capacity signal and said boundary defining signal for setting and storing fixed upper and lower boundary addresses in said module, the range between said upper and lower boundary addresses being determined by the memory capacity of said module; and

range detecting means for comparing a received selectable address with said upper and lower address boundaries and to generate a memory cell selector enabling signal when said received selectable address lies between said upper and lower address boundaries.

19. In a memory controlling module for controlling a memory unit having a number of memory cells, said module having an input and an output,

range calculating means for setting and storing fixed upper and lower boundary addresses in said module, the range between said upper and lower boundary addresses being determined by the memory capacity of said unit,

lower boundary address receiving means for receiving a digital boundary-defining signal in serial form at said input for defining a lower boundary address for said module;

a serial-to-parallel shift register for converting said lower boundary address signal from serial form to parallel form;

a local memory capacity register for to providing a digital memory capacity signal defining the number of memory cells in said memory unit;

adding means for combining said lower boundary signal in parallel form with said memory capacity signal to define a digital upper boundary address signal for said module;

means for storing said lower boundary address signal in parallel form;

means for storing said upper boundary address signal in parallel form;

range detecting means for comparing a received address signal with said upper and lower boundary address signals, and for generating a memory cell selector enabling signal only when the address of said received signal lies between said upper and lower address boundaries.

20. In a memory controlling module as defined in claim 19;

means for receiving a selectable digital absolute address signal that has more digits than said memory capacity signal, said absolute address signal having a range component and a local address component that are partially non-overlapping;

means controlled by the range component of said absolute address signal and said stored boundary address signals for generating said enabling signal for permitting access to memory cells corresponding to the local address component of said absolute address signal only when said absolute address signal lies within a range defined by said boundaries.

21. In an information processing system comprising a plural memory system;

and a processing unit for addressing individual memory cells in such system for selectively storing information therein or for reading information therefrom and in which said memory cells are assigned a series of ordinal symbols to specify their locations, and wherein said memory system comprises a series of memory modules,

each memory module comprising;

a memory unit having a plurality of memory cells, the number of memory cells in each memory module being an integral multiple of an integral base number,

an address range detector for detecting whether a selectable address signal received from said processing unit lies within the ordinal range of said module whereby said selectable address signal from said processing unit actuates a cell in said module only when the cell addressed lies within the range of said module, and

range setting means comprising a range signal source for generating a signal representing the memory capacity of said memory module;

said memory system also comprising means coupling the range setting means of successive memory modules in the series and controlled by signals supplied by said range signal sources for rendering the address range detector corresponding to each memory module responsive only to addresses signals having addresses within range appropriate to each memory module.

22. In an information processing system as defined in claim 21,

an auxiliary range detector controlled by the range setting means of said memory modules for establishing a total range for said latter detector representing the sum of the ranges of said series of memory modules;

and

memory enabling means responsive to said selectable address signal for enabling said memory modules only when said address signal represents a selected address within said total range.

23. In an information processing system including a central processing unit and a plural memory system:

a plurality of memory modules connected to form a memory bank for accessing by a selectable absolute address signal supplied by said processor, each memory module having a memory unit having a number of memory cells and fixed starting and ending addresses and also having a memory range control unit;

a memory capacity register in each module for establishing the range between said fixed starting address and said fixed ending address for cells in the memory unit associated with said module;

power supply means for providing operating voltages to the central processing unit and each memory module and for supplying a hang voltage after being energized;

a start signal generator connected to said power supply means and actuated by said hang voltage;

means connecting said start signal generator to said memory control units to set said memory control units in an initial starting condition;

a starting address generator controlled by said start signal generator, after said initial starting condition has been established, to generate a signal representing a lower boundary address and to apply said lower boundary address to one of said memory modules; and

means controlled by said starting address signal and the memory capacity registers for establishing an upper boundary address for said one memory module and lower and upper boundary addresses for the memory units on the respective remaining modules with the address ranges of the modules contiguous and free of overlap thereby establishing a continuous range of integral absolute addresses for the memory bank formed by said memory units.

24. In a method for addressing individual memory cells for selectively storing information therein or for reading out selected information therefrom, the steps of:

providing a series of individual memory modules, each containing a number of such memory cells;

creating in said memory module a memory capacity signal representing the number of memory cells in the memory module;

combining the memory capacity signals corresponding to memory modules prior to each memory module but the first in the series, to provide a signal representing the sum of the memory capacities of said prior modules,

registering a numerical starting address for each memory module to designate a first memory cell address therein in accordance with the sum signal corresponding to prior modules in the series; and

combining the memory capacity signal of each module with the numerical starting address of each module to establish an ending address for each memory module.

25. In the method for addressing individual memory cells set forth in claim 24, wherein the number of memory cells in each module is equal to the range between starting and ending addresses;

allocating to each memory cell an individual address number.

26. In the method for addressing individual memory cells set forth in claim 25, wherein the address range of each of said module lies between lower and upper boundaries;

presenting a desired memory cell address signal to a module;

comparing said desired memory cell address signal with signals representing the starting and ending addresses of said module;

granting access to a memory cell in said module if said memory cell address lies within the address range of said module, and

denying access to said memory cells on said module when said memory cell address lies outside the address range of said module.

27. In the method for addressing individual memory cells set forth in claim 25, wherein the address range of each of said modules lies between lower and upper boundaries;

presenting a desired memory cell address to each of said modules,

determining the address range with which said desired memory cell address lies;

selecting the module having the address range that includes the desired memory cell address; and

granting access to the addressed memory cell in said selected module.

28. In a modular data processing system:

a mother board having a plurality of multiple contact connectors adapted to cooperate with edge contacts on printed circuit boards;

a plurality of memory modules, each of said plurality of memory modules comprising a printed circuit board having edge contacts adapted to removably cooperate with a corresponding plurality of multi-contact connectors on said mother board, each memory module comprising;

a range calculator having an input and an output and having a memory capacity register for determining the range of addresses of memory cells in said module; and

an address range detector for determining whether a received address is within the range of addresses of that memory module;

and means on said mother board interconnecting contacts on said connectors to connect the output of one range calculator to the input of another range calculator.

29. In the modular data processing system as set forth in claim 28,

a processor module comprising a printed circuit board having edge contacts adapted to removably cooperate with a multi-contact connector on said mother board;

a starting system on said processor module;

means connecting said starting system to the input of a first range calculator to establish a starting address in a first module of said plurality of modules;

and means in said calculators for establishing boundary addresses in successive modules whereby the address ranges of successive modules are contiguous and free to overlap.

30. In a memory system for a digital computer having a series of successively ordered memory modules, address boundary allocation means comprising:

a local memory capacity register in each said memory module, for storing a representation of the memory capacity of said each module, the first module of said series having a predetermined value for its starting address boundary; and

an electrical means interconnecting said successive modules, each said module in the series but the first being responsive to said local memory capacity registers of all prior modules in the series, for automatically establishing a unique starting address boundary for said each memory module.

31. In a memory system for a digital computer as defined in claim 30, said address boundary allocation means further comprising:

activation means for activating said memory system; and

means responsive to said activation means for setting the starting address boundary of the first memory module of the series to said predetermined value and for establishing unique and sequential address boundaries for the remaining memory modules in said series.

32. In an improved memory system for digital computers, a serial array of memory modules comprising:

automatic address boundary setting means in each memory module for establishing fixed beginning and ending addresses of said each memory module to be unique and to be contiguous to the like addresses of adjacent memory modules in said serial array;

said address boundary setting means being interconnected when said modules are in said array whereby they are automatically responsive to the replacement of one module in the array by a replacement module having a different memory capacity for correctly setting said beginning and ending addresses of the replacement module and of each succeeding module in the array.

33. In an improved memory system for digital computers having a plurality of memory units, each having a plurality of addressable memory cells located therein;

and each having an automatic memory address boundary defining means comprising;

lower address boundary means for defining the lower boundary address of each said memory unit and for registering said addresses as respective digital signals;

memory unit capacity means in each respective memory unit for representing the memory capacity of each said respective memory unit and for registering said capacity as a respective digital signal; and

upper address boundary means for summing selected ones of said lower boundary address signals and selected ones of said memory unit capacity signals to determine an upper boundary address signal and for registering said upper boundary address for each said respective memory unit;

means for presenting a desired memory cell address signal to all said memory units for either writing information into said cells or reading information out from said cells; and

means in the respective memory units for granting access to a memory cell in a particular memory unit only if said desired memory cell address signal lies within the upper and lower address boundaries of the said particular memory unit in which said memory cell address is located.

34. in a method for addressing individual memory cells for the selective placement or sensing of information therein, the steps of:

providing a serial array of individual memory modules, each having a plurality of addressable memory cells, and each having a plurality of signal registers;

storing in a register in each memory module a digital signal representing the memory capacity of each said memory module;

registering an ending address in the first module in accordance with the memory capacity of said first module, said first module having a beginning address,

registering the beginning address of each said module but said first module in accordance with the sum of the memory capacities of the prior modules in the series and the beginning address of said first module by electrically combining the digital signals of said prior modules;

registering the ending address of each said module but said first by electrically combining the beginning address of said latter module with the memory capacity signal stored therein;

presenting a selected memory cell address signal to all modules;

comparing the selected address signal with the registered beginning address signals of each module to determine whether said desired memory cell address signal lies within the range of the beginning and ending addresses of each module; and

granting access to a memory cell in a memory module only if said selected memory cell address signal lies within said range of said module.

35. In a digital computer having a processing unit and a system for selectively addressing individual memory cells of a memory bank composed of a series of memory modules, each having a separate memory unit, each memory unit of said series containing a number of such memory cells, for storing information in or for reading information out of each cell in accordance with a corresponding selectable absolute address signal generated by said processing unit to represent an absolute address, the combination of:

starting address means for supplying a signal representing an initial starting address for said memory bank;

each said memory module of said memory bank comprising;

a lower address boundary limiting means for registering a digital signal defining the lower boundary address for said each module;

an upper address boundary limiting means for registering a digital signal defining the upper boundary address for said each module; and

a memory capacity signal source for supplying a digital signal representing the memory cell capacity of said each memory unit;

means responsive to the initial starting address of said memory bank for registering a local starting address in the lower address boundary limiting means of the first memory module of said series;

means controlled by the starting address signal registered in said first memory module of said series and the memory capacity signal supplied by the memory capacity signal source of said first memory module for determining and registering the upper address of said first memory module as an upper address digital signal in the upper address boundary means thereof whereby a first local address range is established for said first memory module;

means for rendering the lower address boundary limiting means of each memory module but the first responsive to the upper address boundary means of the next preceding memory module of the series to determine and to register a lower address digital signal in the lower address boundary limiting means of said each memory module but the first; and

means in each memory module but the first in the series responsive to the starting address signal registered in said each module and to the memory capacity signal supplied by the memory capacity signal source in said each module for determining and registering the upper address digital signal in said upper address boundary defining means in said each module;

whereby a local address range is established for said each memory module but the first, the total address range for said series of modules being greater than the address range for any one module.

36. In a digital computer as defined in claim 35, the combination further comprising:

means for presenting a desired absolute memory cell address signal to said memory modules for either writing information into a cell or reading information out of a cell; and

means in the respective memory modules for granting access to a memory cell in each memory unit of said modules only if said desired memory cell address signal lies within the local address range of the memory module in which said memory cell address is located.

37. In a digital computer as defined in claim 36, the combination further comprising:

means for generating and storing a digital signal defining said total address range of said series of modules;

means for comparing said total address range signal with said desired memory cell address signal; and

means for granting access to a memory cell in said series of modules only if said desired memory cell address signal lies within said total address range.

38. In a digital computer having a processing module and a system for selectively addressing individual memory cells of a plurality of memory units external to said processing module, each such memory unit containing a number of such memory cells for storing information in or for reading information out of each cell in accordance with a corresponding selectable absolute address signal generated by said processing module to represent an absolute address, the improvement wherein the processor module comprises:

a local memory capacity register for storing a capacity signal representing the local memory capacity in said processor module;

a starting address generator for generating a starting address signal corresponding to said memory capacity;

means for transmitting said starting address signal to at least one of said plurality of memory units for establishing a lower address boundary for said one memory unit;

means for receiving and storing an ending address signal from at least one of said plurality of memory units, said ending address signal being representative of the total memory capacity of said plurality of memory units;

means for comparing a selected absolute address signal generated by said processing module, with said starting address signal and with said total memory capacity signal; and

means for granting access to memory cells in said plurality of memory units only when said selected absolute address represented by said selected absolute address signal is greater than said local memory capacity and less than said total memory capacity.

39. In a digital computer as defined in claim 38, the processor module further comprising:

a memory unit, and means for granting access to memory cells in said processor module memory unit only when said selected absolute address represented by said selected absolute address signal is less than said lower address boundary.

40. In a digital computer as defined in claim 38, said plurality of memory units being arranged as an ordered series of memory units, the first memory unit is said series having means for receiving said starting address signal, the last memory unit is said series having means for transmitting said ending address signal, and each memory unit in said series having means for establishing limiting address boundaries corresponding to the limiting address boundaries of the next following and next preceding memory units in said series.

41. In a digital computer having a processing module and a system for selectively addressing individual memory cells of at least one memory unit external to said processing module and containing a number of such memory cells for storing information in or for reading information out of each cell in accordance with a corresponding selectable absolute address signal generated by said processing module to represent an absolute address, the improvement wherein the processor module comprises:

a local memory capacity register for storing a capacity signal representing the local memory capacity in said processor module;

a starting address generator for generating a starting address signal corresponding to said memory capacity;

means for transmitting said starting address signal to said memory unit for establishing a lower address boundary for said memory unit;

means for receiving and storing an ending address signal from said memory unit, said ending address signal being representative of the total memory capacity of said memory unit;

means for comparing a selected absolute address signal generated by said processing module, with said starting address signal and with said total memory capacity signal; and

means for granting access to said memory cells only when said selected absolute address represented by said selected absolute signal is greater than said local memory capacity and less than said total memory capacity.

42. In a digital computer as defined in claim 41, the processor module further comprising:

a memory unit, and means for granting access to memory cells in said processor module memory unit only when said selected absolute address represented by said selected absolute address signal is less than said lower address boundary.

43. In a digital computer as defined in claim 41, said external memory unit having means for receiving said starting address signal, and means for transmitting said ending address signal to said processor module.