Compression testing apparatus

• US 4,027,532 A
• Filed: 04/20/1976
• Issued: 06/07/1977
• Est. Priority Date: 04/20/1976
• Status: Expired due to Term

• Current Assignee: Sun Electronics Corp (Snap-On Incorporated)
• Original Assignee: Sun Electronics Corp (Snap-On Incorporated)
• Inventors: Trussell, Gerald C., Arnston, Robert W.
• Primary Examiner(s): Myracle, Jerry W.
• Application Number:
  US05/678,670
• Time in Patent Office: 413 Days
• Field of Search: 73/117.2, 73/116, 73/115, 235/151.3, 324/19
• US Class Current: 73/114.23
• CPC Class Codes: G01L 23/085 by measuring fluctuations of starter motor current or of battery voltage battery testing arrangements G01R31/36; testing of electrical installation on transport means G01R31/005; battery testing arrangements G01R31/36

Abstract

The disclosure describes apparatus for determining the relative compression of the chambers of an internal combustion engine by analyzing the voltage or current waveform of the starter system during cranking. The waveform is rapidly and repetitively sampled by an analog-to-digital converter which converts the amplitude waveform into corresponding digital signals. A processor selects one of the signals having either a maximum or minimum value to represent each of the chambers. The processor automatically determines the number of chambers in the engine, determines the relative compression of the chambers and displays the result to the operator of the system.

Claims

1. A Apparatus for testing the compression of an internal combustion engine including a first chamber, a second chamber, a first member movable inside the first chamber in order to compress gas within the first chamber during a first time period, a second member movable inside the second chamber in order to compress gas within the second chamber during a second time period, a starter motor for moving the first and second members during a starting period and an electrical system for supplying an electrical power signal to rotate the starter motor during the starting period, and apparatus comprising:

converting means for generating a first group of discrete digital amplitude signals having values proportional to the amplitude of the electrical power signal at a plurality of discrete times during the first time period and for generating a second group of discrete digital amplitude signals having values proportional to the amplitude of the electrical power signal at a plurality of discrete times during the second time period;

processing means for selecting from the first group of discrete digital amplitude signals a first representative signal for representing the compression of the first chamber, for selecting from the second group of discrete digital signals a second representative signal for representing the compression of the second chamber and for generating relative compression digital signal having a value depending on the relative values of the first and second representative signals; and

display means for displaying the value of the relative compression digital signal.

2. Apparatus, as claimed in claim 1, wherein the converting means comprises means for generating digital amplitude signals having values proportional to the current amplitude of the electrical power signal.

3. Apparatus, as claimed in claim 1, wherein the converting means comprises means for generating digital amplitude signals having values proportional to the voltage amplitude of the electrical power signal.

4. Apparatus, as claimed in claim 1, wherein the converting means comprises and analog-to-digital converter.

5. Apparatus, as claimed in claim 1, wherein the converting means generates the digital amplitude signals at the rate of at least 500 per second.

6. Apparatus, as claimed in claim 1, and further comprising timing means for generating and storing a digital timing signal corresponding to each digital amplitude signal and identifying the order in which the digital amplitude signals are generated.

7. apparatus, as claimed in claim 6, wherein the timing means comprises:

a memory location;

means for indexing the memory location in response to the generation of each digital amplitude signal; and

means for resetting the memory location to an initial value at the beginning of the first group and at the beginning of the second group.

8. Apparatus, as claimed in claim 6, wherein the first group of discrete digital amplitude signals comprises a first amplitude signal having a maximum value and a second amplitude signal having a minimum value within the first group and wherein the processor means comprises means for selecting the first amplitude signal as the first representative signal if the timing signals corresponding to the first and second amplitude signals indicate that the first amplitude signal occurred after the second amplitude signal and for selecting the second amplitude signal as the first representative signal if the timing signals corresponding to the first and second amplitude signals indicate that the first amplitude signal occured before the second amplitude signal.

9. Apparatus, as claimed in claim 8, wherein the second group of discrete digital amplitude signals comprises a third amplitude signal having a maximum value and a fourth amplitude signal having a minimum value within the second group and wherein the processor means comprises means for selecting the third amplitude signal as the second representative signal if the timing signals corresponding to the third and fourth amplitude signals indicate that the third amplitude signal occurred after the fourth amplitude signal and for selecting the fourth amplitude signal as the second representative signal if the timing signals corresponding to the third and fourth amplitude signals indicate that the third amplitude signal occurred before the fourth amplitude signal.

10. Apparatus, as claimed in claim 9, wherein the processor means comprises means for storing the first and second representative signals.

11. Apparatus, as claimed in claim 9, wherein the processor means comprises means for calculating the difference between the values of the first and second representative signals.

12. Apparatus, as claimed in claim 1, wherein the display means comprises a cathode ray tube.

13. Apparatus for testing the compression of an internal combustion engine including a plurality of N chambers, members movable within the chambers in order to compress gas within the chambers during N different time periods, a starter motor for moving the members inside the chambers during a starting period and an electrical system for supplying an electrical power signal to rotate the starter motor during the starting period, said apparatus comprising:

converting means for generating N groups of discrete digital amplitude signals having values proportional to the amplitude of the electrical power signal at a plurality of discrete times during the N time periods;

processor means for selecting from the N groups of discrete digital amplitude signals N representative signals A₁ through A_N respectively representing the compression of the N chambers and for calculating a relative compression digital signal R according to the equation;

##EQU2## where Q is a constant.

14. Apparatus, as claimed in claim 13, and further comprising timing means for generating and storing a digital time signal corresponding to each digital amplitude signal and identifying the order in which the digital amplitude signals are generated.

15. Apparatus, as claimed in claim 14, wherein the timing means comprises:

a memory location;

means for indexing the memory location in response to the generation of each amplitude signal; and

means for resetting the memory location to an initial value at the beginning of each of the N groups.

16. Apparatus, as claimed in claim 14, wherein each of the N groups of discrete digital amplitude signals includes a first amplitude signal having a maximum value and a second amplitude signal having a minimum value within the group and wherein the processor means comprises means for selecting the first amplitude signal in each group as the representative signal A for that group if the timing signals corresponding to the first and second amplitude signals indicate that the first amplitude signal occurred after the second amplitude signal and for selecting the second amplitude signal in each group as the representative signal A for that group if the timing signals corresponding to the first and second amplitude signals indicate that the first amplitude signal occurred before the second amplitude signal.

17. Apparatus as claimed in claim 13 wherein the engine employs ignition signals to sequentially ignite fuel-air mixtures in the chambers, and further comprising:

means for generating a synchronizing signal in response to each ignition signal used to ignite the fuel-air mixture in a first one of the chambers;

counting means for counting a synchronizing signal and each ignition signal occurring between two successive synchronizing signals; and

memory means for storing the contents of the counting means after the number of chambers has been counted.

18. Apparatus, as claimed in claim 17, wherein the memory means comprises a separate memory location corresponding to each chamber and an additional memory location for storing the contents of the counting means, whereby data corresponding to each chamber can be separately stored.

19. Apparatus, as claimed in claim 18, wherein the processor means comprises a digital computer which disables the counting means in response to two successive synchronizing signals.

20. Apparatus, as claimed in claim 19, wherein the computer jumps to a preselected program subroutine in response to a hardware interrupt.

21. Apparatus, as claimed in claim 20, wherein the apparatus further comprises means for generating a cylinder signal during the occurrence of each ignition signal used to ignite the fuel-air mixture of a preselected chamber selected by the computer.

22. Apparatus, as claimed in claim 21, wherein a hardware interrupt occurs in response to the simultaneous generation of a cylinder signal and an ignition signal and wherein the counting means is advanced in response to the hardware interrupt.

23. Apparatus, as claimed in claim 17, and further comprising shorting means for preventing the ignition signals from occurring after the contents of the counting means has been transferred to the memory means, whereby the engine can be rotated without starting.

24. Apparatus, as claimed in claim 23, wherein the shorting means comprises a switching device operatively connected to the engine for preventing the ignition signals from occurring in response to a shorting signal.

25. Apparatus, as claimed in claim 24, wherein the processor means comprise means for generating the shorting signal after the contents of the counting means has been transferred to the memory means.

26. Apparatus, for automatically determining the number of chambers in an internal combustion engine in which ignition signals are used to sequentially ignite fuel-air mixtures in the chambers, said apparatus comprising:

means for generating a synchronizing signal in response to each ignition signal used to ignite the fuel-air mixture in a first one of the chambers;

counting means for counting a synchronizing signal and each ignition signal occurring between two successive synchronizing signals;

memory means for storing digital data; and

processing means for transferring the contents of the counting means to the memory means after the number of chambers has been counted.

27. Apparatus, as claimed in claim 26, wherein the memory means comprises a separate memory location corresponding to each chamber and an additional memory location for storing the contents of the counting means, whereby data corresponding to each chamber can be separately stored.

28. Apparatus, as claimed in claim 27, wherein the processing means comprises a digital computer which disables the counting means in response to two successive synchronizing signals.

29. Apparatus, as claimed in claim 28, wherein the computer jumps to a preselected program subroutine in response to a hardware interrupt.

30. Apparatus, as claimed in claim 29, wherein the apparatus further comprises means for generating a cylinder signal during the occurrence of each ignition signal used to ignite the fuel-air mixture of a preselected chamber selected by the computer.

31. Apparatus, as claimed in claim 30, wherein a hardware interrupt occurs in response to the simultaneous generation of a cylinder signal and an ignition signal and wherein the counting means is advanced in response to the hardware interrupt.

32. Apparatus, as claimed in claim 26, and further comprising shorting means for preventing the ignitions signals from occurring after the contents of the counting means has been transferred to the memory means, whereby the engine can be rotated without starting.

33. Apparatus, as claimed in claim 32, wherein the shorting means comprises a switching device operatively connected to the engine for preventing the ignition signals from occurring in response to a shorting signal.

34. Apparatus, as claimed in claim 33, wherein the processor means comprise means for generating the shorting signal after the contents of the counting means has been transferred to the memory means.