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Memory with error detection and correction means

  • US 4,028,539 A
  • Filed: 11/20/1975
  • Issued: 06/07/1977
  • Est. Priority Date: 12/09/1974
  • Status: Expired due to Term
First Claim
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1. A memory comprising:

  • a first plurality of memory units, a first input address line connected to said memory units for delivering a first partial address thereto, said first plurality of memory units having valid partial addresses in a first partial address sequence from a specified first to a specified second memory unit;

    a second input address line connected to said memory units for addressing individual bits of one of said memory units;

    a data input register connected to said plurality of memory units;

    a data output register connected to said plurality of memory units;

    a detection device connected to said data output register for detecting a non correctable storage error and producing an output signal;

    an inversion device connected to said first input address line for inverting predetermined address bits, thereby allowing addressing of said first plurality of memory units in a second partial address sequence starting from a third memory unit;

    an inversion control device, having an input connected to said detection device, and an output connected to said inversion device for activating said inversion device; and

    blocking means for blocking addressing of ones of a second plurality of memory units beyond a predetermined fourth memory unit, said blocking means and said inversion control device being linked for blocking addressing of a faulty memory unit in said second plurality of memory units.

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