Planar process for making high frequency ion implanted passivated semiconductor devices and microwave integrated circuits

• US 4,030,943 A
• Filed: 05/21/1976
• Issued: 06/21/1977
• Est. Priority Date: 05/21/1976
• Status: Expired due to Term

• Current Assignee: Hughes Aircraft Company (Rtx Corporation)
• Original Assignee: Hughes Aircraft Company (Rtx Corporation)
• Inventors: Lee, Don H., Thrower, William F., Weller, Kenneth P.
• Primary Examiner(s): Rutledge, L. Dewayne
• Assistant Examiner(s): Davis, J. M.
• Application Number:
  US05/688,662
• Time in Patent Office: 396 Days
• Field of Search: 148/1.5, 357/56, 357/58, 357/81
• US Class Current: 438/122
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 29/864 Transit-time diodes, e.g. IMPATT, TRAPATT diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/10158 at the passive surface
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

The specification describes new high frequency ion implanted semiconductor devices, novel microwave integrated circuits employing same, and a planar fabrication process for both wherein initially an ion implantation and PN junction passivation mask is formed on one surface of a semiconductor substrate. Next, a heavily doped buried region is ion implanted through an opening in the mask and into the substrate to a preselected controlled depth. Thereafter, one or more additional ion implants are made through the mask opening to complete the active device regions and a PN junction therebetween, all of which are bounded by an annular, higher resistivity unimplanted region of the semiconductor substrate. The PN junction thus formed terminates beneath the implantation and passivation mask, and the semiconductor substrate is then annealed to remove ion implantation damage and to electrically activate the ion implanted regions, while simultaneously controlling the lateral movement of the PN junction beneath the passivation mask. Such annealing does not adversely affect the conductivity and passivation characteristics of either the higher resistivity region or the passivation mask. Openings to the heavily doped buried regions in the substrate are made both opposite and coaxial to the openings in the passivation mask. Precision in the area and depth of these contact openings is achieved by use of a chemical etchant that is preferential to the substrate crystallographic orientation and the impurity concentration levels. Ohmic contact metallization is deposited into the contact openings after which the heat sink metallization is applied to either or both of the metallized contact regions. A mesa is formed to provide discrete structures with the implanted device region surrounded by a ring of high-resistivity semiconductor and thick low-loss dielectric. The resultant device structure exhibits a small degradation in high frequency performance relative to comparable state of the art unpassivated devices.

Claims

1. A planar process for fabricating high frequency semiconductor devices including the steps of:

a. providing a high-resistivity semiconductor substrate,

b. forming an insulating ion implantation mask on the surface of said substrate,

c. implanting conductivity type determining ion species through an opening in said mask and into said substrate to form a buried region therein,

d. selectively implanting additional ion species above said buried region to thereby form a semiconductor device and including a region thereof extending to the surface of said substrate,

e. removing a selected region of said substrate to thereby expose at least a portion of said buried region, and

f. making ohmic contacts to both said buried region and said implanted region extending to the substrate surface, whereby appropriate operating or modulating bias or control potentials may be applied to said ohmic contacts to control the flow of microwave energy from said semiconductor device.

2. The process defined in claim 1 which also includes:

a. selectively etching said substrate to thereby remove portions of said substrate adjacent the ion implanted regions thereof to control parasitic losses in said substrate, and

b. bonding heat sink metallization to said ohmic contacts for providing heat sinking of said semiconductor device on both sides of said substrate.

3. The process defined in claim 1 which further includes:

a. implanting an additional buried region in said substrate to thereby provide another ohmic contact location for another semiconductor device in said substrate,

b. selectively implanting additional ion species above said additional buried region to thereby form multiple diverse semiconductor devices in said substrate,

c. removing a selected region of said substrate underlying said additional buried region to thereby expose at least a portion of said additional buried region, and

d. making ohmic contacts to said additional buried region and to the exposed ion implanted substrate surface region aligned therewith, respectively, so that operating or modulating potentials may be applied to said multiple diverse semiconductor devices which together control the flow of microwave energy in said substrate.

4. The process defined in claim 3 which further includes depositing a control metallization pattern or patterns between ohmic contacts for said multiple diverse semiconductor devices for establishing the path or paths of energy flow therebetween.