Keyhole-less electronic lock

• US 4,031,434 A
• Filed: 12/29/1975
• Issued: 06/21/1977
• Est. Priority Date: 12/29/1975
• Status: Expired due to Term

• Current Assignee: Eastern Company The
• Original Assignee: Eastern Company The
• Inventors: Trombly, John E., Perron, Robert Richard
• Primary Examiner(s): Envall, Jr., R. N.
• Application Number:
  US05/644,947
• Time in Patent Office: 540 Days
• Field of Search: 317/134, 340/274 C, 340/147 F, 340/147 MD, 318/162, 70/277, 70/278
• US Class Current: 361/172
• CPC Class Codes: G07C 2009/00634 Power supply for the lock
• CPC Class Codes: G07C 2009/00777 by induction
• CPC Class Codes: G07C 9/00182 operated with unidirectional data transmission between data carrier and locks
• CPC Class Codes: G07C 9/22 in combination with an identity check of the pass holder
• CPC Class Codes: G07C 9/29 the pass containing active electronic elements, e.g. smartcards
• CPC Class Codes: G07F 7/0866 by active credit-cards adapted therefor G07F7/1008 takes precedence
• CPC Class Codes: Y10T 70/7062 Electrical type [e.g., solenoid]

Abstract

An inductively coupled electronic lock system wherein a key unit receives binary multiple bit data and generates a binary frequency modulated carrier which is input to a transmitter inductor. A lock unit of the system has an inductive pick-up which compares the received sequence of binary signals with a predetermined sequence of binary signals so that upon a proper correspondence a motor opens the lock.

Claims

1. An electronic lock system comprising, in combination:

key means including generating means for generating a plurality of binary frequency modulated carrier waves, first inductor means electrically connected to said generating means;

lock means including lock inductor means positioned to inductively couple with said key inductor means when said key means is in predetermined spatial relation to said lock means, signal distinguishing means electrically connected in circuit of said lock means and disposed to receive signals from said generating means whereby a predetermined sequence of binary signals is compared with the sequence of binary signals contained within the carrier from said generating means, motor means electrically connected in driven relation to said signal distinguishing means so that upon a corresponding comparison of said signal distinguishing means said motor means is activated, lock lug means connected in movable, driven relation to said motor means, whereby activation of said motor means causes movement of said lock lug means between a locked and unlocked position.

2. An electronic lock system as in claim 1 wherein said generating means further comprises first memory means operative to store an electrically alterable multiple bit key code, oscillator means connected to the output of said first memory means so that binary electrical pulses comprising the key code are converted to an output of a binary frequency-modulated carrier wave, first amplifier means providing amplification of carrier having an input connected to output of said oscillator means, said first amplifier means having an output and input connected to said key inductor means, and first logic means having two outputs with one output to said first memory means and another output to said oscillator means, whereby said first logic means controls timing of transfer of binary data to said oscillator means and enables oscillator means.

3. An electronic lock system as in claim 2 wherein said first logic means further comprises first clock means having output connected to said first memory means, whereby said first clock means provides clock signal to said first memory means for shifting data bits of the key code to said oscillator means, first binary counter means connected to output of said clock, whereby first counter means counts clock pulses and first flip flop means including start switch with said first flip flop means having one input connected to said first counter means and three outputs with one electrically connected to first counter means and another connected to said first clock means and the final one connected with said oscillator means, whereby setting said first flip flop means with said switch means enables said oscillator means and said clock means and after all data bits have been shifted from said first memory means counter means resets said first flip-flop with said first flip flop in turn resetting said first counter means to zero.

4. A lock system as in claim 2 wherein said signal distinguishing means further comprises capacitor means connected across said second inductor means so as to provide sufficient reasonance and to smooth transmitted signals, first and second diode means connected to said lock inductor means to generate a direct current supply of power to said lock means, receiver means connected to output of said lock inductor means so that the carrier wave comprising the key code is received and converted to a binary electrical pulse signal;

second memory means having input connected to the output of said receiver means so as to receive and store the key code, programable code memory means having stored therein master lock code, comparator means being operative to provide an output signal upon receipt of the key code from said second memory means corresponding to said master lock code received from said programable code memory means, power storage means connected to the output of first and second diode means, whereby said power storage means stores sufficient energy to operate said motor means, motor controller means having input connected to said power storage means and having input and output connected to said motor means, whereby said motor controller means upon receipt of a trigger signal activates said motor means, second logic means having input connected to receiver means and three outputs with one connected to said second memory means and another connected to said comparator means and the last one connected to said motor controller means, whereby said second logic means provides timing for the ordering of multiple bit data in said second memory means and enables said comparator means and upon receipt of signal from said comparator means sends a trigger signal to said motor controller means.

5. A lock system as in claim 4 wherein said second logic means comprises second clock means having input connected to said receiver means so that said second clock means receives a synchronization pulse and output connected to said second memory means for providing a clock pulse to order multiple bit data within said second memory means, second counter means having input connected to said second clock means so as to receive and count clock pulses and output connected to said comparator means so as to enable comparator means, and second flip flop means having input connected to said comparator means and two outputs with one connected to said motor controller means and the other connected to said second counter means, whereby upon receipt of signal from said comparator means of a corresponding code comparision said second flip-flop will be reset so as to send a triggering signal to said motor controller means and a triggering signal to said second counter means for resetting said second counter means to zero.

6. A lock system as in claim 5 wherein said second counter means has an output connected to the input of said second clock means, whereby upon lack of correspondence between the key code and the master code said second counter disables second clock means.