DC to AC inverter with unregulated input and regulated output

• US 4,032,832 A
• Filed: 07/14/1975
• Issued: 06/28/1977
• Est. Priority Date: 07/14/1975
• Status: Expired due to Term

• Current Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Original Assignee: Bunker Ramo Corporation
• Inventors: Miller, Frank Donald
• Primary Examiner(s): Beha, Jr., William H.
• Application Number:
  US05/595,486
• Time in Patent Office: 715 Days
• Field of Search: 321/9 R, 321/18, 321/27 MS, 321/DIG. 1
• US Class Current: 363/43
• CPC Class Codes: H02M 7/49 Combination of the output voltage waveforms of a plurality of converters

Abstract

An inverter for producing regulated AC voltage from an unregulated DC voltage source, such as a battery, employs two stepped voltage waveform generating means independently controlled in phase to produce waveform outputs that approach sine waves which are additively combined to produce an AC output voltage whose amplitude is sensed to produce a feedback signal for comparison with a reference voltage to produce an error signal that causes one stepped waveform generating means to so shift in phase relative to the other as to reduce the error. Each stepped voltage waveform generating means is capable of producing at least half the total desired AC output voltage, so that the DC voltage source may drop by as much as 50% and the desired AC output voltage can still be maintained by shifting the relative phase between the stepped waveforms.

Claims

1. A DC to AC inverter for an unregulated DC voltage source comprising

two stepped waveform generating means connected to said source, each stepped waveform generating means being capable of delivering from said source one half the total desired voltage amplitude in the form of phase displaced, digitally controlled, stepped waveforms that approach a sine wave, each of said waveform generating means comprising a source of clock pulses at a substantially constant frequency and a step counter responsive to said clock pulses for timing said steps;

means for additively combining said stepped waveforms to produce an output voltage,

means for sensing said output voltage and producing a feedback signal proportional to its amplitude,

means for comparing said feedback signal with a reference signal to produce an error signal proportional to the difference therebetween, and

means responsive to said error signal for inhibiting said clock pulses from reaching the step counter of one of said two-stepped waveform generating means, thereby phase shifting the stepped waveform of one stepped waveform generating means relative to the other to reduce said error signal.

2. The combination of claim 1 wherein each stepped waveform generating means is further comprised of at least two power bridges, each having an output transformer for selectively delivering a voltage of either polarity across a secondary winding and means for selectively connecting the ends of primary windings of said transformers to positive and negative terminals of said DC voltage source in response to states of said step counters, and wherein said secondary windings of said transformers are connected in series.

3. The combination of claim 2 wherein a step up ratio is preselected for each transformer such that, when voltages are selectively induced and additively combined across said series connected secondary windings, said stepped waveform approaches a sine wave.

4. The combination of claim 2 wherein said stepped waveform generating means generates said stepped waveforms in six steps with voltage levels of ±

V₁, ±

V₂ and ±

(V₁ +V₂), and is comprised of two power bridges, each having an output transformer for selectively delivering a voltage of either polarity across a secondary winding, and means for selectively connecting the ends of primary windings of said transformers to positive and negative terminals of said voltage source, one transformer having a step up turn ratio of about 2.68X;

1 for the voltage ±

V₂ and the other having a step up turn ratio of X;

1 for the voltage ±

V₁, where X is a selected value.

5. The combination of claim 2 wherein said stepped waveform generating means generates said stepped waveforms in six steps with voltage levels of ±

V₁, ±

V₂ and ±

(V₁ +V₂), and is comprised of two groups of similar power bridges, one group of five having a transformer in each, and one group of two having a transformer in each, each transformer having the same voltage step up turn ratio and its secondary winding connected in series with the secondary windings of all other transformers.

6. An inverter for producing regulated AC voltage at a desired amplitude level from an unregulated DC voltage source comprising

two stepped waveform generating means for producing from said DC voltage separate stepped waveforms approaching a sine wave at the same frequency, each step being equal to said DC voltage multiplied by some predetermined constant, each of said waveform generating means comprising a source of clock pulses at a substantially constant frequency and a step counter responsive to said clock pulses for timing said steps;

means for additively combining said separate stepped waveforms to produce an AC output voltage,

means for sensing and filtering said output voltage to produce a DC feedback signal proportional to the amplitude of said AC output voltage,

means for comparing said feedback signal with a reference signal to produce an error signal when the amplitude of said output voltage is below said desired level, and

means responsive to said error signal for inhibiting said clock pulses from reaching the step counter of one of said two-stepped waveform generating means, thereby shifting the phase of one of said stepped waveform generating means relative to the other to reduce said error signal.

7. Apparatus as defined in claim 6 wherein each stepped waveform generating means is capable of producing at least half the total desired AC voltage amplitude whereby said DC voltage source may drop by as much as fifty percent and the desired output voltage amplitude can still be maintained by shifting the phase of one stepped waveform generating means relative to the other.

8. Apparatus as defined in claim 7 wherein each stepped waveform generating means is comprised of at least two power bridges, each having an output transformer for selectively delivering a voltage of either polarity across a secondary winding and means for selectively connecting the ends of primary windings of said transformers to positive and negative terminals of said DC voltage source, and wherein said secondary windings of said transformers are connected in series.

9. Apparatus as defined in claim 8 wherein a step up ratio is preselected for each transformer such that, when voltages are selectively induced and additively combined across said series connected secondary windings, said stepped waveform approaches a sine wave.

10. Apparatus as defined in claim 9 wherein said DC voltage source is a battery source and including means for initiating operation of said two stepped waveform generators 180°

out of phase whenever power from said inverter is turned on to be applied to a load, whereby said desired output voltage level is always approached from below, and is always maintained at said desired level as said battery discharges and its DC output voltage drops.

11. In combination,

an unregulated DC voltage source coupled to a load by a pair of means for generating stepped waveforms at the same frequency, each generating means comprising a source of clock pulses at a substantially constant frequency, a step counter responsive to said clock pulses, and a count decoding means connected to said step counter for timing and controlling the amplitude of said steps of each stepped waveform generating means, each stepped waveform generating means being comprised of two transformers having turn ratios of X:

1 and about 2.68X;

1 and being capable of delivering six-step waveforms of half the desired AC voltage to said load, and said pair of stepped waveform generating means producing two phase displaced stepped waveforms, each stepped waveform approximating a sine wave,

means for additively combining said two stepped waveforms,

means for sensing the amplitude of the AC voltage applied to said load,

means responsive to said sensing means for generating an error signal proportional to the amplitude difference between the AC voltage applied to said load and said desired AC voltage, and

means responsive to said error signal for adjusting the relative phase shift between said two stepped waveforms, to reduce said error signal toward zero.

12. The combination of claim 11 wherein said phase adjusting means includes a first circuit for adjusting the phase of one stepped waveform relative to the other when said reference signal exceeds said feedback signal, and for adjusting the phase of the other stepped waveform relative to said one stepped waveform when said feedback signal exceeds said reference signal.

13. In combination,

an unregulated DC voltage source coupled to a load by a pair of means for generating stepped waveforms at the same frequency, each generating means comprising a source of clock pulses at a substantially constant frequency and a step counter responsive to said clock pulses for timing said steps of each stepped waveform generating means, and each generating means being capable of delivering half the desired AC voltage to said load, said pair of stepped waveform generating means producing two phase displaced stepped waveforms, each stepped waveform approximating a sine wave,

means for additively combining said two stepped waveforms,

means for sensing the amplitude of the AC voltage applied to said load,

means responsive to said sensing means for generating an error signal proportional to the amplitude difference between the AC voltage applied to said load and said desired AC voltage, and

means responsive to said error signal for adjusting the relative phase shift between said two stepped waveforms, to reduce said error signal toward zero, wherein said adjusting means is comprised of means responsive to said error signal for inhibiting said clock pulses from reaching the step counter of one of said two stepped waveform generating means.

14. The combination of claim 13 wherein said inhibiting means operates to inhibit only one clock pulse every predetermined number of cycles of one of said step counters.

15. The combination of claim 13 wherein said inhibiting means is comprised of a cycle counter for counting said predetermined number of cycles, an exclusive-OR circuit having one input terminal connected to said source of clock pulses and another input terminal connected to the output of said cycle counter, and means for coupling the output of said exclusive-OR circuit to the step counter of one of said stepped waveform generating means,

16. The combination of claim 15 wherein said DC voltage source is a battery source and including means for initiating operating of said stepped waveform generators 180°

out of phase whenever power from said battery source is turned on to be applied to said load, whereby said desired AC voltage to said load is always approached from below, and is maintained as said battery source discharges and its DC voltage drops.