Apparatus for processing interrupts in microprocessing systems

• US 4,034,349 A
• Filed: 01/29/1976
• Issued: 07/05/1977
• Est. Priority Date: 01/29/1976
• Status: Expired due to Term

• Current Assignee: Sperry Rand Corporation
• Original Assignee: Sperry Rand Corporation
• Inventors: Derchak, Nicholas, Monaco, Robert F.
• Primary Examiner(s): Chapnick, Melvin B.
• Application Number:
  US05/653,409
• Time in Patent Office: 523 Days
• Field of Search: 340/172.5, 445/1
• US Class Current: 710/48
• CPC Class Codes: G06F 13/26 with priority control
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

Circuitry external of a microprocessor determines priority between different peripheral devices requesting interrupts to generate a restart vector and a signal granting priority to one of the interrupt-requesting devices. The peripheral device loads its status and address into two addressable registers connected to a common system bus. The restart vector is loaded into the instruction register of the microprocessor. The microprocessor treats the restart vector as an instruction to store the contents of the program counter in memory and loads certain bits of the restart vector into the program counter. These bits represent the starting address of a subroutine of eight instructions for analyzing the interrupt. An interrupt is recognized and the status and identification of the interrupting device is stored in a single instruction cycle. On the next instruction cycle the first instruction of the interrupt analysis routine may begin. During this analysis routine the contents of the two addressable registers may be read out to determine which device caused the interrupt and what action should be taken in view of the status of the interrupting device. Provision is made for processing interrupts other than those requested by peripheral devices, and each type of interrupt generates a different restart vector thus selecting a different address as the first instruction address of the interrupt analysis routine.

Claims

1. A data processor system comprising:

a central processor including means for executing a sequence of instructions;

memory means for storing instructions and data;

a peripheral device including means for generating a peripheral device interrupt signal when communication between said central processor and said peripheral device is desired;

a common system bus connected to said central processor and said memory means;

control means connected to said common system bus for controlling said peripheral device;

said control means including means responsive to a peripheral device interrupt signal for placing an interrupt request signal on said common system bus, and means responsive to a bus grant signal on said common system bus for simultaneously placing the status and address of the peripheral device requesting an interrupt on said common system bus;

first means connected to said common system bus for generating a bus grant signal on said common system bus in response to an interrupt request signal thereon;

second means responsive to an interrupt request signal on said common system bus for generating a central processor interrupt signal;

an address register and a status register connected to said common system bus; and

,

means responsive to said central processor interrupt signal for enabling said address and status registers to thereby load said address and status registers with the address and status of the peripheral device requesting the interrupt.

2. A data processor system as claimed in claim 1 wherein said central processor is a microprocessor and said address and status regusters are external of said microprocessor.

3. A data processor system as claimed in claim 1 and further comprising:

third means responsive to an interrupt request signal on said common system bus for applying a restart vector to said central processor; and

,

means in said central processor for addressing said memory with said restart vector to obtain the next instruction to be executed.

4. A data processor system as claimed in claim 1 and having a plurality of peripheral devices each including means for generating a peripheral device interrupt signal, said peripheral devices being connected to said control means for control thereby.

5. A data processor system as claimed in claim 1 wherein said means for enabling said address and status registers includes means responsive to said central processor interrupt signal for generating an interrupt acknowledge signal, and means responsive to said interrupt acknowledge signal for loading said address and status registers during the same instruction cycle that said interrupt acknowledge signal is generated.

6. In a data processing system of the type having a central processor means connected by a common bus means to a plurality of access means, said access means selectively controlling access of a plurality of peripheral devices to said common bus means for the transfer of data between said peripheral devices and said common bus means, each said access means further including means responsive to a peripheral interrupt request for generating an interrupt request signal and means responsive to a bus grant signal for placing the address and status of the peripheral device making an interrupt request on said common bus means, the improvement comprising:

priority encoder means responsive to interrupt request signals from said access means for applying a bus grant signal to the access means granted priority;

means connected to said priority encoder means for generating a processor interrupt request signal in response to said interrupt request signals;

means in said central processor responsive to said processor interrupt request signal for producing an interrupt acknowledge signal;

restart vector generating means connected to said priority encoder means and responsive to said interrupt acknowledge signal for generating and applying a restart vector to said common bus means;

first and second addressable registers connected to said common bus means for receiving and storing the status and address placed on the common bus means by the access means granted priority; and

,

means responsive to said interrupt acknowledge signal for gating the status and address from the common bus means into said first and second addressable registers.

7. The improvement as claimed in claim 6 wherein said central processor means includes means connected to said common bus means for utilizing said restart vector as the address of the next instruction to be executed following said interrupt.

8. The improvement as claimed in claim 6 and further comprising:

means responsive to said interrupt acknowledge signal for controlling said priority encoder means so that the bus grant signal is applied to the access means granted priority during the interval said restart vector is applied to said common bus means, and, gating means in said common bus means and responsive to said interrupt acknowledge signal for preventing the mixing of the address and status from said access means with said restart vector.

9. The improvement as claimed in claim 6 wherein said restart vector generating means comprises:

a further priority encoder means;

means for applying interrupt signals indicative of various system conditions to said further priority encoder means, one of said signals being from said priority encoder means,

said further priority encoder means determining the highest priority system condition requesting an interrupt and generating a multibit value representing the highest priority system condition;

first means responsive to said multibit value for generating said restart vector;

second means responsive to said multibit value for generating an interrupt acknowledge signal for the system condition granted priority, said second means disabling the generation of said bus grant signal if the system condition granted priority is not an interrupt request signal from said access means.

10. The improvement as claimed in claim 9 and further comprising a memory connected to said common bus means, and wherein said access means comprises a plurality of direct memory access controllers for controlling the transfer of data between said memory and said peripheral devices.

11. The improvement as claimed in claim 6 wherein said common system bus means includes a system address bus and a system data bus, said first addressable register having inputs connected to said system address bus for receiving an address from said access means and outputs connected to said system data bus, said second addressable register having inputs responsive to said system data bus for receiving status from said access means and outputs also connected to said system data bus.