Electronic timer
First Claim
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1. An electronic timer comprising:
- pulse generating means for providing at a selected rate a train of evenly spaced, in time, pulses;
memory means comprising;
a plurality of storage locations accessible at an even rate in a fixed order of succession,loading means responsive to input pulses for serially loading, in the order of said succession, data bits in at least any two said storage locations, andreadout means coupled to said storage locations and responsive to evenly spaced, in time, pulses from said pulse generating means for successively accessing, one storage location per pulse, in said fixed order of succession and providing pulse outputs from those of said storage locations in which data bits are stored, said pulse outputs thus being spaced in time in accordance with the position in sequence of the storage locations in which data bits are stored, and in accordance with the rate of said input pulses;
address means coupled to said memory means and responsive to said train of pulses from said pulse generating means for referencing the position in said memory means of at least one of said locations of said memory means; and
actuating means responsive to an output of said readout means for controlling work.
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Abstract
An electronic timer for selectively timing the occurrence of electrically controllable events. The relative time spacing of events to be timed is stored or programmed in a memory by proportional storage in memory locations. This having been accomplished, execution of the program is effected by means of a selectable rate pulse generator which interrogates the memory. At those locations where positive data is stored, there results an output which is employed to perform a switching function.
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10 Claims
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1. An electronic timer comprising:
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pulse generating means for providing at a selected rate a train of evenly spaced, in time, pulses; memory means comprising; a plurality of storage locations accessible at an even rate in a fixed order of succession, loading means responsive to input pulses for serially loading, in the order of said succession, data bits in at least any two said storage locations, and readout means coupled to said storage locations and responsive to evenly spaced, in time, pulses from said pulse generating means for successively accessing, one storage location per pulse, in said fixed order of succession and providing pulse outputs from those of said storage locations in which data bits are stored, said pulse outputs thus being spaced in time in accordance with the position in sequence of the storage locations in which data bits are stored, and in accordance with the rate of said input pulses; address means coupled to said memory means and responsive to said train of pulses from said pulse generating means for referencing the position in said memory means of at least one of said locations of said memory means; and actuating means responsive to an output of said readout means for controlling work. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification