Supervisor address key control system
First Claim
1. A supervisor addressability control system for controlling the quantity of limited addressability available to a supervisor and to a user in a main memory, comprisinga status register having a first bit position providing a supervisor state signal for indicating whether the system is in supervisor state or not, and a second bit position providing an alternate protect mode (APM) signal indicating whether the system is in the alternate protect mode or not,a user address key register (UKR) for containing an address key that makes available to a processor a user'"'"'s addressability in the main memory which may contain the user'"'"'s programs and data,supervisor/user addressability switching AND gate means having inputs receiving the supervisor state signal, the APM signal, and an instruction fetch signal provided by the processor, an output of the switching AND gate means being enabled when the APM mode, supervisor state, and instruction fetch input signals all exist simultaneously, the output being disabled when any input signal is not activated,key-providing AND gate means having one input connected to the output of the UKR, and another input connected to an inverted output of the switching AND gate means,whereby the output state of the key-providing AND gate means provides the supervisor address key while the switching AND gate means is disabled so that an instruction must be fetched within the supervisor addressability, and provides the user address key while the switching AND gate means is enabled which occurs while the supervisor is not fetching an instruction so that an executing supervisor instruction can access operand(s) within the user addressability.
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Abstract
System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).
The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory.
However, if the APM bit is off while the supervisor bit is on, all instruction and operand storage accesses can only be made in the supervisor key area, regardless of whether the supervisor key or user key is in the UKR. Hence no user area is accessible to the supervisor.
But, if the supervisor bit is off, all instruction and operand accesses can only be made in the user area of the key in the UKR. Hence the supervisor programs cannot execute.
23 Citations
6 Claims
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1. A supervisor addressability control system for controlling the quantity of limited addressability available to a supervisor and to a user in a main memory, comprising
a status register having a first bit position providing a supervisor state signal for indicating whether the system is in supervisor state or not, and a second bit position providing an alternate protect mode (APM) signal indicating whether the system is in the alternate protect mode or not, a user address key register (UKR) for containing an address key that makes available to a processor a user'"'"'s addressability in the main memory which may contain the user'"'"'s programs and data, supervisor/user addressability switching AND gate means having inputs receiving the supervisor state signal, the APM signal, and an instruction fetch signal provided by the processor, an output of the switching AND gate means being enabled when the APM mode, supervisor state, and instruction fetch input signals all exist simultaneously, the output being disabled when any input signal is not activated, key-providing AND gate means having one input connected to the output of the UKR, and another input connected to an inverted output of the switching AND gate means, whereby the output state of the key-providing AND gate means provides the supervisor address key while the switching AND gate means is disabled so that an instruction must be fetched within the supervisor addressability, and provides the user address key while the switching AND gate means is enabled which occurs while the supervisor is not fetching an instruction so that an executing supervisor instruction can access operand(s) within the user addressability.
Specification