Supervisor address key control system

• US 4,035,779 A
• Filed: 04/30/1976
• Issued: 07/12/1977
• Est. Priority Date: 04/30/1976
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hood, Robert Allen, Davis, Michael Ian, Birney, Richard Eugene, Wise, Larry Edward, McDermott, Thomas Stephen
• Primary Examiner(s): Thomas, James D.
• Application Number:
  US05/681,985
• Time in Patent Office: 438 Days
• Field of Search: 340/172.5
• US Class Current: 711/164
• CPC Class Codes: G06F 12/1458 by checking the subject access rights

Abstract

System mode controls for obtaining limited addressability for supervisor programming operations without disturbing a user address key currently contained in a user key register (UKR).

The mode controls are provided by bits in a system register called a level status register (LSR), which include an APM bit, and a supervisor state bit. The largest supervisor addressability is obtained when both the APM and supervisor state bits are set on, which permits execution of a supervisor program which can access user data and programs. In more detail, each instruction fetch must be in the supervisor key area, identified by a predetermined supervisor key value which is not in the UKR, while each operand of the fetched supervisor instruction is accessed in the user key area identified by the current key in the UKR. The supervisor is not permitted to access any user area which does not have its key in the UKR. Thus, the supervisor can be prevented from having addressability over part or all of the main memory.

However, if the APM bit is off while the supervisor bit is on, all instruction and operand storage accesses can only be made in the supervisor key area, regardless of whether the supervisor key or user key is in the UKR. Hence no user area is accessible to the supervisor.

But, if the supervisor bit is off, all instruction and operand accesses can only be made in the user area of the key in the UKR. Hence the supervisor programs cannot execute.

Claims

1. A supervisor addressability control system for controlling the quantity of limited addressability available to a supervisor and to a user in a main memory, comprising

a status register having a first bit position providing a supervisor state signal for indicating whether the system is in supervisor state or not, and a second bit position providing an alternate protect mode (APM) signal indicating whether the system is in the alternate protect mode or not,

a user address key register (UKR) for containing an address key that makes available to a processor a user'"'"'s addressability in the main memory which may contain the user'"'"'s programs and data,

supervisor/user addressability switching AND gate means having inputs receiving the supervisor state signal, the APM signal, and an instruction fetch signal provided by the processor, an output of the switching AND gate means being enabled when the APM mode, supervisor state, and instruction fetch input signals all exist simultaneously, the output being disabled when any input signal is not activated,

key-providing AND gate means having one input connected to the output of the UKR, and another input connected to an inverted output of the switching AND gate means,

whereby the output state of the key-providing AND gate means provides the supervisor address key while the switching AND gate means is disabled so that an instruction must be fetched within the supervisor addressability, and provides the user address key while the switching AND gate means is enabled which occurs while the supervisor is not fetching an instruction so that an executing supervisor instruction can access operand(s) within the user addressability.

2. A supervisor addressability control system as defined in claim 1, having

Or circuit means with an input connected to the output of the switching AND gate means, and

inverter means connected between the output of the OR circuit means and the input to the key-providing AND gate means.

3. A supervisor addressability control system as defined in claim 2, further including

means connecting the supervisor state signal to an input of the OR circuit means,

whereby when the supervisor state signal is not indicating the supervisor state the inverter means continuously enables the key-providing AND gate means to output the user address key, which provides user addressability and inhibits supervisor addressability.

4. A supervisor addressability control system as defined in claim 3, further comprising

user AND gate means having an input receiving the supervisor state signal provided by the first bit position in the status register,

Apm inverting means connecting the APM signal to a second input of the user AND gate means,

whereby when the APM signal is off while the supervisor state signal is on, the user AND gate means is continuously enabled to continuously disable the key-providing AND gate means through the inverter means, so that the key-providing AND gate means continuously outputs the supervisor key and only supervisor addressability is available to the processor.

5. A supervisor addressability control system as defined in claim 1, further comprising

an active address key select circuit having one input connected to the output of the key-providing AND gate means,

a plurality of I/O subchannels each having cycle steal key registers, and channel priority means selecting a cycle steal key from one of the cycle steal key registers during an access request by a corresponding subchannel, the cycle steal key being provided to another input of the active address key select circuit.

6. A supervisor addressability control system as defined in claim 5, further comprising

an I/O access cycle input line connected to an input of the active address key select circuits, a cycle steal cycle signal on the I/O access cycle input line outgating the cycle steal key from the select circuit to a main memory bus for providing addressability for a current cycle steal storage access,

a processor access cycle input line also connected to an input of the active address key select circuits, a processor access cycle signal on the processor access cycle input line being provided after the end of any simultaneous cycle steal cycle signal to outgate to the main memory bus a supervisor or user address key currently being provided by the key-providing AND gate means to provide addressability for a processor storage access.