Information processing system

• US 4,037,212 A
• Filed: 01/20/1976
• Issued: 07/19/1977
• Est. Priority Date: 01/31/1975
• Status: Expired due to Term

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Hotta, Shinkichi, Nomiya, Kosei, Tsuiki, Takao, Kobayashi, Takeshi
• Primary Examiner(s): Nusbaum, Mark E.
• Application Number:
  US05/650,764
• Time in Patent Office: 546 Days
• Field of Search: 445/1, 340/172.5
• US Class Current: 713/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 15/02 manually operated with input through keyboard and computation using a built-in program, e.g. pocket calculators

Abstract

In an information processing system controlled systematically by a programable logic array, the initialization of the contents of a predetermined memory circuit after switching-on the power is effected by setting the contents of the memory circuit to an initial value by means of a signal generated automatically or manually.

Claims

1. In an information processing system including:

a memory in which a microprogram for processing information is stored;

an address register for designating the addresses of program information stored in said memory;

a plurality of storage circuits coupled to said memory and selectively receiving program information stored in said memory; and

means, coupled to said storage circuits and said address register, for setting the contents of said storage circuits at prescribed values upon the turn-on of said system;

the improvement wherein said means comprises

first means for generating a first prescribed signal upon the turn-on of said system,

second means, coupled to said first means and said address register, for coupling said first prescribed signal to a plurality of selected bit positions of said address register corresponding to a plurality of selected addresses of said memory, and

wherein said plurality of selected addresses of said memory have been programmed to store said prescribed values for setting the contents of said storage circuits, and

third means, coupled to said address register, for selectively addressing individual ones of the bit positions of said plurality of selected bit positions of said address register, and thereby causing the contents of the individual ones of said selected addresses of said memory to be coupled to respective ones of said plurality of storage circuits.

2. The improvement according to claim 1, wherein said memory includes a microprogram logic array for selectively supplying control signals to said storage circuits, said microprogram logic array comprising a plurality of control output lines for supplying said control signals thereover, a plurality of address lines to which address signals for designating the addresses of matrix positions in said array are applied, and a matrix of coupling elements selectively connected to said address lines and said control output lines and providing prescribed control signals on selected control output lines in response to the receipt of address signals on selected address lines.

3. The improvement according to claim 2, wherein said memory further includes an address decoder having a plurality of address drive lines respectively connected to the address lines of said microprogram logic array, a plurality of bit position input lines respectively connected to the bit positions of said address register, and a matrix of further coupling elements selectively connected to said address drive lines and said bit position input lines for decoding the signals produced on said bit position input lines and producing an address signal on a selected one of said address drive lines in accordance with the state of the bit positions of said address register.

4. The improvement according to claim 1, wherein said first means comprises a flip-flop which is placed in a prescribed one of its stable states upon the turn-on of said system.

5. The improvement according to claim 4, further comprising means for resetting said flip-flop into the other of its stable states after the turn-on of said system, thereby removing said first prescribed signal from said second means and said address register.

6. The improvement according to claim 5, wherein said microprogram logic array and said address decoder are comprised of a read-only memory.

7. The improvement according to claim 3, further including a plurality of latch circuits coupling said control output lines to said storage circuits, and wherein selected ones of said latch circuits are connected to respective bit positions of said address register.

8. The improvement according to claim 3, wherein said address register has n bit positions and wherein said plurality of selected bit positions of said address register is less than n and constitute the most significant m bit positions of said address register.

9. The improvement according to claim 8, further comprising means for sequentially effecting binary addressing of the least significant n--m bit positions of said address register to thereby sequentially designate the individual ones of said plurality of selected addresses of said memory and cause said prescribed values to be sequentially applied to respective ones of said storage circuits.