Pulse code modulation compressor

• US 4,037,226 A
• Filed: 01/07/1976
• Issued: 07/19/1977
• Est. Priority Date: 01/07/1976
• Status: Expired due to Term

• Current Assignee: E-Systems Incorporated (Rtx Corporation)
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: Betts, William L., Greene, Robert T.
• Primary Examiner(s): Miller, Charles D.
• Application Number:
  US05/647,298
• Time in Patent Office: 559 Days
• Field of Search: 340/347 DD, 325/38 R, 325/38 B
• US Class Current: 341/75
• CPC Class Codes: H03G 7/007 of digital or coded signals
• CPC Class Codes: H03M 7/50 Conversion to or from non-linear codes, e.g. companding

Abstract

A pulse code modulation compressor converts linear pulse code modulation words into companded pulse code modulation words. A read only memory is loaded with a conversion table and used to perform successive approximations for the conversion. The converted output is then passed through a double buffer to allow independent operation of the conversion clock and output clock.

Claims

1. A pulse code modulation compressor for companding pulse code modulation signals having a sign bit, comprising:

A. a magnitude comparator for comparing pulse code modulation signals having first and second inputs and decision outputs;

B. a first shift register connected to said first comparator input and having an input;

C. a memory having an address input and a pulse code modulation output programmed to convert compressed pulse code modulation signals to linear pulse code modulation signals, said memory output connected to said second comparator input;

D. a second shift register having a single stage set of bit cells equal in number to the number of bits in a compressed pulse code modulation word and a sign bit cell to be processed, said word bit cells connected to said comparator decision outputs;

E. a logic circuit connected between said magnitude comparator and said second shift register comprising;

1. a first NAND gate having one input terminal connected to the sign bit at said magnitude comparator first input and another input connected to one said magnitude comparator decision output;

2. a second NAND gate connected through an inverter to said sign bit at said magnitude comparator first input and having another input connected to another of said magnitude comparator decision outputs;

3. a third NAND gate having an input connected to said first NAND gate and a second input connected to said second NAND gate and having an output connected to each bit cell of said address register except the most significant bit cell through a second inverter; and

F. clock means connected to said second register to provide a series of successively more accurate memory address pulse code modulation words in said second register.

2. A pulse code modulation compressor as specified in claim 1, wherein said clock means comprises a ring counter which sends a sequence of clock signals sequentially to the set of bit cells in said address register beginning with the most significant bit cell and progressing to the least significant bit cell.

3. A pulse code modulation compressor as specified in claim 1, wherein said most significant bit cell is connected to said sign bit at said first shift register input.

4. In combination with the pulse code modulation compressor specified in claim 1, a third shift register connected to said second shift register to receive and transfer companded pulse code modulation signals generated in said second shift register.

5. In combination with the pulse code modulation compressor specified in claim 1, a fourth shift register connected to said third shift register to transfer companded pulse code modulation signals generated in said third shift register in response to an external signal and only when companded pulse code modulation signals are not being generated in said third shift register.