Zone plate alignment marks
First Claim
1. A mask member for use in fabricating microminiature devices, said member comprising a relatively transparent substrate having a selectively patterned relatively opaque layer disposed on said substrate, said selectively patterned layer having formed therein at least one alignment mark pattern, said alignment mark pattern, when illuminated by incident radiation, forming a focused image in a reference plane that is spaced apart a predetermined distance from said forming means.
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Accused Products
Abstract
Certain classes of patterns, for example so-called zone plates, are utilized as alignment marks in the fabrication of integrated circuits. Such a plate, which functions as a lens, provides a high-brightness image that is relatively insensitive to any degradation of the pattern.
94 Citations
12 Claims
- 1. A mask member for use in fabricating microminiature devices, said member comprising a relatively transparent substrate having a selectively patterned relatively opaque layer disposed on said substrate, said selectively patterned layer having formed therein at least one alignment mark pattern, said alignment mark pattern, when illuminated by incident radiation, forming a focused image in a reference plane that is spaced apart a predetermined distance from said forming means.
- 3. A wafer member adapted to have formed on the surface thereof multiple microminiature devices, said member comprising a semiconductor substrate and an alignment mark pattern formed on the surface of said substrate, said pattern, when illuminated by incident radiation, forming a focused image in a reference plane that is spaced apart a predetermined distance from said forming means.
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5. In the fabrication of integrated circuits, a method for aligning a semiconductor wafer, said method comprising the steps of
forming on a portion of the surface of said wafer a pattern that when illuminated by incident radiation forms a high-intensity focused image at a prescribed distance from said surface in a reference plane, directing radiation at said pattern, and moving the surface of said wafer in a plane parallel to said reference plane until said image is detected to occur in a predetermined location in said reference plane.
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7. In the fabrication of integrated circuits, a method for aligning a mask member with respect to a semiconductor wafer, said method comprising the steps of
forming patterns on said mask and wafer that when illuminated by incident radiation form respective high-intensity focused images at prescribed distances from said mask and wafer in a reference plane, directing radiation at said patterns, and varying the relative positions of said mask and wafer until said images are detected to occur in a predetermined location in said reference plane.
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9. Apparatus for aligning a semiconductor wafer of the type that includes on a surface portion of the wafer means that when illuminated by incident radiation forms a high-intensity focused image at a prescribed distance from said surface in a reference plane,
said apparatus comprising: -
a movable table for carrying said wafer, means for directing radiation at said forming means on said wafer thereby to form a high-intensity focused image in said reference plane, and means responsive to the location of said image in said plane for applying control signals to said table to move said wafer to a predetermined position. - View Dependent Claims (10)
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11. Apparatus for aligning a mask member with respect to a semiconductor wafer, said mask member and said wafer including on a surface portion thereof means that when illuminated by incident radiation forms respective high-intensity focused images at prescribed distances from said mask and wafer in a reference plane, said apparatus comprising
means for directing radiation at said forming means thereby to form focused images in said plane, and means responsive to the relative locations of said images in said plane for varying the relative positions of said mask and wafer until said images are detected to occur in a predetermined location in said reference plane.
Specification