High density wafer contacting and test system

• US 4,038,599 A
• Filed: 12/30/1974
• Issued: 07/26/1977
• Est. Priority Date: 12/30/1974
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hubacher, Eric M., Bove, Ronald
• Primary Examiner(s): Demeo, Palmer C.
• Assistant Examiner(s): Karlsen, Ernest F.
• Application Number:
  US05/537,514
• Time in Patent Office: 939 Days
• Field of Search: 324/158 F, 324/158 P, 324/158 R, 324/73 R, 324/72.5
• US Class Current: 324/754.11
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/2853 Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections G01R31/31717 takes precedence; test of chip-to-PCB or lead-to-PCB connections G01R31/66
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A contactor structure employed in a high speed electronic test system for testing the electrical integrity of the conductive paths (or lines) in the packaging substrate prior to the mounting and connection thereto of the high circuit density monolithic devices. The contactor structure includes a semiconductor space transformer fabricated by large scale integration techniques and containing a plurality of discrete first integrated circuits. The first integrated circuits of the space transformer being respectively electrically connected to said electrical probes. Second integrated circuitry interconnecting said first integrated circuits is also contained within said semiconductor space transformer. Under control of said test system said second integrated circuitry selectively energizes, selected first and second ones of said first integrated circuits. Each of said first integrated circuits contains circuitry, whereby said selected first and second ones of said first circuits will manifest the electrical integrity of the electrical path there between.

Claims

1. A space transformer for use in an electronic test system for testing micro-miniature electronic devices, said space transformer comprising:

a monolithic silicon structure;

said silicon structure containing, a first binary decoder circuit adapted to receive a first set of m binary inputs and provide a first set of 2^m binary outputs, a second binary decoder circuit adapted to receive a second set of m binary inputs and provide a second set of 2^m binary outputs, a third binary decoder circuit adapted to receive a third set of m binary inputs and provide a third set of 2^m binary outputs, a fourth binary decoder circuit adapted to receive a fourth set of m binary inputs and provide a fourth set of 2^m binary outputs, where m may be any integer number, a plurality of logic circuits selectively connected to said outputs of said first, second, third and fourth binary decoders, an array of exposed conductive pads connected to said plurality of logic circuits.

2. A space transformer for use in an electronic test system for testing micro-miniature electronic devices as recited in claim 1 further characterized in that said plurality of logic circuits is equal in number to m².

3. A space transformer for use in an electronic test system for testing micro-miniature electronic devices as recited in claim 2 further characterized in that each of said m² logic circuits is connected to a discrete output of each of said first, second third and fourth binary decoders, whereby each of said m² logic circuits is uniquely connected to said first, second, third and fourth binary decoders, whereby said first, second, third and fourth sets of m binary inputs may be employed to select and condition a predetermined first and second ones of said m² logic circuits.

4. A space transformer for use in an electronic test system for testing micro-miniature electronic devices as recited in claim 3 wherein each of said m² logic circuits is essentially identical to each other one of said m² logic circuits and said predetermined first one of said m² logic circuits is adapted to perform a first function and said predetermined second one of said m² logic circuits is adapted to perform a second function.

5. In an electronic test system for electrically testing very small electronic structures, a contactor structure for making electrical contact with an electrical structure undergoing test, said contactor comprising:

a space transformer as recited in claim 4;

a probe assembly electrically and mechanically mated with said contactor structure, said probe assembly having a plurality of probes each of said probes being in electrical contact with one of said array of exposed conductive pads of said space transformer.