Non-translatable storage protection control system

• US 4,038,645 A
• Filed: 04/30/1976
• Issued: 07/26/1977
• Est. Priority Date: 04/30/1976
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Birney, Richard Eugene, Davis, Michael Ian
• Primary Examiner(s): Thomas, James D.
• Application Number:
  US05/682,224
• Time in Patent Office: 452 Days
• Field of Search: 340/172.5
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1458 by checking the subject access rights

Abstract

Combines a storage protect key stack with an access key register (AKR) and active access key (AAK) select circuits. Storage key entries in the stack correspond to the physical blocks in main memory. This combination can provide storage protection for different storage access types within address sub-ranges in the main memory associated with respective access keys. The sub-ranges are blocks of addresses within the full range of addresses of the physical memory. The protect key operation applies to physical addresses, and it obtains system addressing compatibility with an address translation operation using the same access keys as address keys with program logical addresses.

Special features include a shared protect key, which need not be loaded in the AKR, to make specified sub-range(s) shareable by all users of the system, so that any user can access the blocks in memory associated with the shared protect key. For I/O accesses, an override is provided which ignores any read-only control of any memory block to which an I/O access is requested. Supervisor accesses can be made in all key areas, regardless of the AAK, the protect keys, or the read-only flag bits.

Claims

1. A protectable storage system for a main memory comprised of physical blocks, the blocks having respective address sub-ranges within the overall physical address range of the main memory, comprising

key register means having at least an instruction access key register section and an operand access key register section,

storage access request means in a processor for sensing and signalling each type of storage access request made by the processor, the detectable types of request signals including an instruction fetch signal and at least one type of operand access signal, each request signal being for accessing a specified physical address in the main memory, storage request selection means for granting an instruction fetch or operand access request signal to have access to storage,

active key selection means being actuated by a granted instruction fetch request signal or a granted operand access request signal to outgate the content of a corresponding key register section as an active accesss key, the active access key being associated with the specified physical address corresponding to the active access key,

a storage key stack comprised of a plurality of storage key registers respectively assigned to the blocks in the main memory, each register having a key field for containing a storage key assigned to the respective block,

means for outputting a storage key in a selected storage key register in the stack, the register being selected by means of a high-order field in a specified physical address which is the address providing the request signal actuating the active key selection means to outgate the active access key,

a comparator means comparing the outputted storage key from the selected storage key register with the active access key outputted by the active key selection means to provide a compare-equal signal when the compared keys are equal, and a non-compare signal when they are not equal,

whereby the access at the specified address within a key protected sub-range may be allowed if a compare-equal signal is outputted by the comparator means.

2. A protectable storage system as defined in claim 1, further including

each storage key register in the stack also having a read-only flag bit position for further controlling accesses to its address sub-range,

a storage-write control circuit having an input connected to the read-only flag bit position in the selected storage key register, and having another input connected to a storage-write line from the processor which signals when the current storage request is for a write operation in the main memory, an allow-storage-write output of the storage- write control circuit being actuated by a write signal on the storage-write line while the read-only bit input indicates no read-only state for the block to be accessed, and

gate means having inputs connected to the output of the comparator means and to the allow-storage-write output, an output of the gate means providing an allow-access signal when the compare-equal and allow-storage-write signals are being provided.

3. A protectable storage system as defined in claim 2, further including

a shared-area logic circuit having inputs connected to the storage key output of the selected storage key register to receive each outputted key, another input of the logic circuit being connected to the allow-storage-write output, the logic circuit being enabled by a predetermined key value and an allow-storage-write signal to provide a shareable-area output signal in response to the predetermined key and no read-only state for the block being accessed,

whereby the content of each block corresponding to the predetermined key value is shareable by different programs for at least read-only access, while the programs also can have any of their instructions or operands in non-shareable areas.

4. A protectable storage system as defined in claim 3, further including means for making the protectable storage system operationally compatible with an address key translation system, comprising

a circuit for processor selection of non-translation or translation storage protection having inputs signalling whether a translator is installed, whether the translator is enabled, and whether storage protection is enabled, and a non-translation protection enabled output of the circuit being activated when its non-translation input is enabled and its storage protection input is enabled,

and the non-translation protection enabled output being connected as another input to the gate means and as another input to the shared-area logic circuit to disable their operation if the address key translation system is enabled.

5. A protectable storage system as defined in claim 4, further including

a supervisor state line from the processor to signal if the processor is in supervisor state or not,

Or circuit means having inputs connected to the supervisor state line and to the output of the shared-area logic circuit to enable each access request during supervisor state, regardless of the operation by the logic circuit.

6. A protectable storage system as defined in claim 5, further including

a cycle-steal state line from a storage priority select circuit to signal when a currently granted access request cycle is for an I/O cycle steal operation,

another input to the gate means for enabling its output to allow the current access request for the cycle-steal operation, regardless of the read-only state for the block being accessed.