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Divide-by-N/2 frequency division arrangement

  • US 4,041,403 A
  • Filed: 07/28/1975
  • Issued: 08/09/1977
  • Est. Priority Date: 07/28/1975
  • Status: Expired due to Term
First Claim
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1. A frequency divider circuit for deriving two output pulses for every N input pulses where N is an odd number comprising:

  • a source of pulses,gating means having two operating states and a pair of inputs selectively actuatable to switch from either of said states to the other thereof, a third input connected to said source and an output terminal for reproducing said input pulses at said output terminal in one of said states and for inverting said input pulses at said output terminal in the other of said states,synchronous counter means having an input connected to said gating means output terminal and selectively operated in response to a receipt of each group of (N+1)/2 of said reproduced and of said inverted input pulses from said output terminal for producing an output pulse, said counter means including,a plurality of J-K flip-flops each having a J data input, a K data input, a clock input and logic outputs,means for interconnecting particular ones of said data inputs and said outputs of said plurality of flip-flops, andmeans connecting said clock inputs of each of said flip-flops in parallel to said gating means output terminal for changing the state of individual ones of said flip-flops in response to a receipt of a pulse from said gating means output terminal synchronously to increment a pulse count, andtoggle switch means having outputs connected selectively to actuate one of said pair of inputs of said gating means and an input responsive to a receipt of said counter means output pulse for effecting a toggling of said switch means to switch the state of said gating means and for effecting the inverting of said pulses at said gating means output terminal to yield two equally spaced output pulses upon the receipt of two of said groups of (N+1)/2 pulses at said output terminal.

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