Signal analyzer system

• US 4,041,461 A
• Filed: 07/25/1975
• Issued: 08/09/1977
• Est. Priority Date: 07/25/1975
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dennis, Charles A., Wallis, Donald E., Sproul, William W. III, Walendziewicz, Eugene T., Kratz, Gary L.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Rhoads, Jan E.
• Application Number:
  US05/599,306
• Time in Patent Office: 746 Days
• Field of Search: 445/1, 340/172.5
• US Class Current: 712/10
• CPC Class Codes: G06F 9/3877 using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

A signal analyzer system is disclosed which includes an arithmetic processor containing a plurality of pipeline processor elements in parallel array with each element connected to a respective working store, with all of the elements being under microprogram control of an arithmetic element controller.

A storage controller included in the system is connected to the arithmetic processor, to a system input and to a system ouput.

A bulk storage included in the system is connected to the storage controller. The storage controller controls data transfers into and out of the system and between the bulk storage and arithmetic processor.

A control processor included in the system is connected to the arithmetic processor and the storage controller by means of a data bus for centrally controlling the operation of the plurality of pipeline processor elements by transmitting micro control words over the bus.

Claims

1. A digital computer system comprising:

an arithmetic processor containing a plurality of pipelined processor arithmetic elements in parallel array with each element connected to a respective working store for temporarily storing data, with all of the elements being connected to and under microprogram control of an arithmetic element controller, for arithmetically processing said data;

said arithmetic element controller including an arithmetic element control store for storing arithmetic element microinstructions and a memory address register connected to an address input of said arithmetic element control store for accessing said arithmetic element microinstruction;

a bulk store for storing said data and said arithmetic element microinstructions prior to the time of an initial microprogram load into said arithmetic processor;

a storage controller connected to said bulk store and to said working store and said arithmetic element control store in said arithmetic processor for selectively transferring said arithmetic element microinstructions from said bulk store to said arithmetic element control store in response to a first transfer command word and selectively transferring said data from said bulk store to said working store in response to a second transfer command word;

a control processor connected to an input of said memory address register in said arithmetic element controller and to said storage controller by means of an external bus, for sending said first transfer command word to said storage controller at said initial microprogram load time to load said microinstructions into said control store, for sending a first control store address to said memory address register after said load time to initiate execution by the microprogram in said arithmetic processor, and for subsequently sending said second transfer command word to said storage control during execution time, to transfer said data to said working store;

whereby the control processor is free to carry out supervisory and data management functions during said execution time and the program storage and data storage functions are separated during execution time, minimizing storage bandwidth requirements.

2. The system of claim 1, wherein said control processor further comprises:

a program store for storing emulated machine language instruction and data;

a writable control store for storing microprogram control instructions;

an arithmetic unit connected to said program store and said control store, for accessing microprogram instructions for said control store in response to functionally coded emulated machine language instructions input from said program store, and decoded as general and supervisory instructions, as data transfer instructions to be output on said external data bus, as input/output instructions to be output on said external data bus, or as arithmetic operational instructions to be output on said external bus.

3. The system of claim 2 wherein said arithmetic unit fetches microinstructions from said writable control store and fetches machine language instructions and data from and stores data into said program store.

4. The system of claim 3 wherein said control processor further comprises:

an operand bus;

a plurality of local storage registers connected to said operand bus;

said external bus connected to said operand bus;

a first external register located in said storage controller connected to said external bus;

a second external register located in said arithmetic processor, connected to said external bus;

said operand bus connected to said arithmetic unit;

whereby said arithmetic unit may access one of said external registers over said external bus in the same manner as it would access one of said local registers in said local store.

5. The system of claim 4 wherein said accessing of an external register takes place over an extended microinstruction cycle.

6. The system of claim 2, wherein said control store comprises a high speed memory and said program store comprises a low speed memory.

7. The system of claim 2, wherein said program store comprises a first group of memory pages having an even address and a second group of memory pages having an odd address;

means for sequentially accessing an even page and an odd page from said first and second groups;

whereby the effective access time for said program store is reduced.

8. The system of claim 2, wherein said program store and said control are connected to a direct memory access channel which is connected to said storage controller,

whereby pages of stored data may be selectively transferred by said storage controller between said program store or said control store in said control processor and said bulk store.

9. The system of claim 8, wherein said direct memory access bus is connected to a system input and output for transferring the contents of said program store, said control store, or said bulk store, there between.

10. The system of claim 1, wherein said arithmetic processor further comprises:

said arithmetic element controller connected to said external bus;

whereby programmed control instructions generated in said control processor are transmitted over said external bus commanding multistep operations to be executed by said arithmetic element controller by carrying out arithmetic operations in said arithmetic elements.

11. The system of claim 10, wherein said arithmetic element controller contains a micro storage for storing microprogram instructions to execute the multistep operations commanded by the control processor;

whereby after a microprogram has been initially loaded in said micro storage and the control processor commands an operation by means of said external bus, said arithmetic element controller provides full processing control over said arithmetic processor, including all data transfer between said arithmetic elements and said working storage, thereby freeing the control processor from signal processing tasks.

12. The storage of claim 10, wherein said arithmetic element further comprises:

a two'"'"'s complement multiplier having an input connected to said working store;

a three input arithmetic logic unit having augend and addend inputs connected to said working store and said multiplier;

said arithmetic unit having its sum output connected to said working store;

whereby said arithmetic element operates in a pipelined fashion with new operands entering each stage of execution in the pipe in sequential fashion.

13. The system of claim 10, wherein said arithmetic element further comprises:

an input connected to said working store;

a left multiplier register and a right multiplier register having inputs connected to said input line;

a two'"'"'s complement multiplier having a multiplier input connected to said left register and a multiplicand input connected to said right register;

a left adder input register, a center adder input register, and a right adder input register, having an input connected to the product output of said multiplier;

said left adder input register and said center adder input register having a second input connected to said working store;

a scale factor register having a first input connected to said external bus and a second input connected to said working store;

a first prescaler having a data input connected to said left adder input register and a control input connected to said scale factor register;

a second prescaler having a data input connected to said center adder input register and a control input connected to said scale factor register;

a third prescaler having a data input connected to said right adder input register and a control input connected to said scale factor register;

a three input arithmetic logic unit having a first input connected to the output of said first prescaler, a second input connected to the output of said second prescaler, and a third input connected to the output of said third prescaler;

a post scaler having a data input connected to the sum output of said arithmetic logic unit and a control input connected to said scale factor register;

a center adder output register and a right adder output register having inputs connected to the sum output of said arithmetic logic unit;

said post scaler having an output connected to a left adder output register which in turn has an output connected to said first prescaler;

said center adder output register having an output connected to said second prescaler and said right adder output register having an output connected to said third prescaler;

said post scaler having an output connected to a rounder which in turn has an output connected to an input of said left multiplier register and said right multiplier register;

an arithmetic element output register having an input connected to said rounder and an output connected to said working store;

whereby said arithmetic element operates in a pipelined fashion at staging rate such that new operands enter each stage of execution in the pipe in consecutive time intervals.

14. The system of claim 1, wherein said working store further comprises:

a left working store memory having a left address input line connected to said arithmetic element controller;

a right working store memory having a right address input line connected to said arithmetic element controller;

a first two by two switch having a first data input connected to the output of said arithmetic element, a second data input connected to said storage controller, a first data output line connected to said left working store memory and a second data output line connected to said right working store memory;

a second two by two switch having a first data input connected to said left working store memory and a second data input connected to said right working store memory, a first output connected to the input of said arithmetic element and a second output connected to said storage controller;

said first two by two switch and second two by two switch having a control input line connected to said arithmetic element controller for controlling the operation of said left working store memory and said right working store memory;

whereby during the period when the left working store memory is communicating with said arithmetic element, the right working store memory may communicate with said storage controller, and vice versa.

15. The system of claim 1, wherein said arithmetic element controller of said arithmetic processor further comprises:

a branch register connected to said external data bus for storing microprogram addresses used on unconditional branch operations;

a branch and count register connected to said external bus for storing microprogram addresses used on conditional branch operations;

said branch register containing a branch address field;

said branch and count register containing a count field, a reset field, and a branch address field;

said count field specifying the number of said conditionl branch operations to be performed before transferring the next process step;

said reset field specifying a reset value for the count to be reinitialized a plurality of times in a nested loop application;

a microprogram address register having an input connected to said branch register and said branch and count register for storing a branch address;

a microprogram storage having an address input connected to said microprogram address register for control and a data input connected to said storage controller for storing microprogram instructions for the operation of said arithmetic element and said working storage, accessible by said microprogram address;

whereby the independent execution of data conditional operations in each of a plurality of arithmetic elements operating in parallel, may proceed under the common control of said arithmetic element controller without the loss of simultaneity of operation of the arithmetic elements.

16. The system of claim 1, wherein said arithmetic element controller further comprises:

a microprogram address register having an input connected to said external bus;

a micro storage having an input connected to said storage controller;

a microinstruction register and decode logic having an input connected to said micro storage;

an address generation logic having an input connected to said microinstruction register and decode logic;

said address generation logic having an output connected to said working store;

said microinstruction register and decode logic having an output connected to said arithmetic unit;

a timing generator connected to said arithmetic unit and said working store;

said micro store having a cycle rate equal to the logic delay of one unit in the pipeline processor of said arithmetic unit;

a portion of each microinstruction issued from said micro storage to said microinstruction register and decode logic being used to control, on successive cycles, the operation of said pipeline processor in said arithmetic unit;

said working store having an accessing cycle which is an integral multiple of said unit of logic delay;

said microinstruction having a second portion controlling the address generation logic for accessing said working store once every said integral multiple of said unit of logic delay.

17. The system of claim 16, wherein said arithmetic element controller further comprises:

said working storage being divided into a left memory and a right memory with a memory address switching means controlling data flow into and out of said left memory and said right memory in response to a control signal generated by said address generation logic over a control line connecting said switching means to said address generation logic;

said arithmetic element controller controlling data transfer between the left half memory of said working store and said arithmetic element when said right half memory of said working store is engaging in data transfers with said bulk storage, and vice versa.

18. The system of claim 1, wherein said storage controller further comprises:

a storage transfer control connected to said external bus, with input and output lines connected to said working store, for providing working store addresses for data words being transferred between said bulk store and said working store;

a priority control connected to said storage transfer controller and having an output connected to said bulk store, for accepting bulk store addresses from said storage transfer control for all working store and control processor data transferred to said bulk store;

an error control having an input connected to said storage transfer control and input and output lines connected to said bulk store, and a bidirectional error control data bus connected to said control processor, for making single error correcton and double error detection of all data received from said bulk store.

19. The system of claim 18, wherein said storage transfer control further comprises:

said storage transfer control controlling the transfer of data between said bulk store and said working store, between said bulk store and said micro store of said arithmetic element controller, and between said bulk store and said control processor;

said storage transfer control operating under control of commands received over said external bus from said control processor;

a control section containing a status word register connected to said external bus and a queue register connected to said external data bus for queuing commands received therefrom;

a rescaler section connected to said error control and to said working store for performing a zero to eight bit left shift on a half word basis on data transferred from said working store to said error control.

20. The system of claim 1, which further comprises:

a direct memory access bus connecting said program storage and control storage in said control processor to said storage controller, for directly accessing data stored in said control processor;

an error control data bus connected between said storage controller and said control processor, for transmitting data;

whereby parallel control can be maintained by said control processor over said storage controller, said bulk storage, and said arithmetic processor.

21. The system of claim 11, wherein said arithmetic element controller generates parallel control signals to operate a plurality of arithmetic elements in parallel;

whereby the number of arithmetic elements controlled by the arithmetic element controller can be expanded without requiring a change in said microprogram instructions.

22. A digital computer system comprising:

an arithmetic processor containing a pipelined processor arithmetic element connected to a working store for temporarily storing data, connected to and under microprogram control of an arithmetic element controller, for arithmetically processing said data;

said arithmetic element controller including an arithmetic element control store for storing arithmetic element microinstructions and a memory address register connected to an address input of said arithmetic element control store for accessing said arithmetic element microinstruction;

a bulk store for storing said data and said arithmetic element microinstruction prior to the time of an initial microprogram load into said arithmetic processor;

a storage controller connected to said bulk store and to said working store and said arithmetic element control store in said arithmetic processor for selectively transferring said arithmetic element microinstructions from said bulk store to said arithmetic element control store in response to a first transfer command word and selectively transferring said data from said bulk store to said working store in response to a second transfer command word;

a control processor connected to an input of said memory address register in said arithmetic element controller and to said storage controller by means of an external bus, for sending said first transfer command word to said storage controller at said initial microprogram load time to load said microinstructions into said control store, for sending a first control store address to said memory address register after said load time to initiate execution by the microprogram in said arithmetic processor, and for subsequently sending said second transfer command word to said storage control during execution time, to transfer said data to said working store;

whereby the control processor is free to carry out supervisory and data management functions during said execution time and the program storage and data storage functions are separated during execution time, minimizing storage bandwidth requirements.

23. The system of claim 22, wherein said control processor further comprises:

a program store for storing emulated machine language instruction and data;

a writable control store for storing microprogram control instructions;

an arithmetic unit connected to sid program store and said control store, for accessing microprogram instructions for said control store in response to functionally coded, emulated machine language instructions input from said program store, as general and supervisory instructions, s data transfer instructions to be output on said external data bus, as input/output instructions to be output on said external data bus, or as arithmetic operational instructions to be output on said external bus.

24. The system of claim 23 wherein said arithmetic unit fetches microinstructions from said writable control store and fetches machine language instructions and data and stores data into said program store.

25. The system of claim 24 wherein said control processor further comprises:

an operand bus;

a plurality of local storage registers connected to said operand bus;

said external bus connected to said operand bus;

a first external register located in said storage controller connected to said external bus;

a second external register located in said arithmetic processor, connected to said external bus;

said operand bus connected to said arithmetic unit;

whereby said arithmetic unit may access one of said external registers over said external bus in the same manner as it would access one of said local registers in said local store.

26. The system of claim 25 wherein said accessing of an external register takes place over an extended microinstruction cycle.

27. The system of claim 23, wherein said control store comprises a high speed memory and said program store comprises a low speed memory.

28. The system of claim 23, wherein said program store comprises a first group of memory pages having an even address and a second group of memory pages having an odd address;

means for sequentially accessing an even page and an odd page from said first and second groups;

whereby the effective access time for said program store is reduced.

29. The system of claim 23, wherein said program store and said control store are connected to a direct memory access channel which is connected to said storage controller;

whereby pages of stored data may be selectively transferred by said storage control between said program store or said control store in said control processor and said bulk store.

30. The system of claim 29, wherein said direct memory access bus is connected to a system input and output for transferring the contents of said program store, said control store, or said bulk store, there between.

31. The system of claim 22, wherein said arithmetic processor further comprises:

said arithmetic element controller connected to said external bus;

whereby programmed control instructions generated in said control processor are transmitted over said external bus commanding multistep operations to be executed by said arithmetic element controller by carrying out arithmetic operations in said arithmetic elements.

32. The system of claim 31, wherein said arithmetic element controller contains a micro storage for storing microprogram instructions to execute the multistep operations commanded by the control processor;

whereby after a microprogram has been initially loaded in said micro storage and the control processor commands an operation by means of said external bus, said arithmetic element controller provides full processing control over said arithmetic processor, including all data transfer between said arithmetic element and said working storage, thereby freeing the control processor from signal processing tasks.

33. The system of claim 22, wherein said working store further comprises:

a left working store memory having a left address input line connected to said arithmetic element controller;

a right working store memory having a right address input line connected to said arithmetic element controller;

a first two by two switch having a first data input connected to the output of said arithmetic element, a second data input connected to said storage controller, a first data output line connected to said left working store memory and a second data output line connected to said right working store memory;

a second two by two switch having a first data input connected to said left working store memory and a second data input connected to said right working store memory, a first output connected to the input of said arithmetic element and a second output connected to said storage controller;

said first two by two switch and second two by two switch having a control input line connected to said arithmetic element controller for controlling the operation of said left working store memory and said right working store memory;

whereby during the period when the left working store memory is communicating with said arithmetic element, the right working store memory may communicate with said storage controller, and vice versa.

34. The system of claim 22, wherein said storage controller further comprises:

a storage transfer control connected to said external bus, with input and output lines connected to said working store, for providing working store addresses for data words being transferred between said bulk store and said working store;

a priority control connected to said storage transfer controller and having an output connected to said bulk store, for accepting bulk store addresses from said storage transfer control for all working store and control processor data transferred to said bulk store;

an error control having an input connected to said storage transfer control and input and output lines connected to said bulk store, and a bidirectional error control data bus connected to said control processor, for making single error correction and double error detection of all data received from said bulk store.

35. The system of claim 34, wherein said storage transfer control further comprises:

said storage transfer control controlling the transfer of data between said bulk store and said working store, between said bulk and said micro store of said arithmetic element controller, and between said bulk store and said control processor;

said storage transfer control operating under control of commands received over said external bus from said control processor;

a control section containing a status word register connected to said external bus and a queue register connected to said external data bus for queuing commands received therefrom;

a rescaler section connected to said error control and to said working store for performing a zero to eight bit left shift on a half word basis on data transferred from said working store to said error control.

36. The system of claim 22, which further comprises:

a direct memory access bus connecting said program storage and control storage in said control processor to said storage controller, for directly accessing data stored in said control processor;

an error control data connected between said storage controller and said control processor, for transmitting data;

whereby parallel control can be maintained by said control processor over said storage controller, said bulk storage, and said arithmetic processor.

37. The system of claim 22, wherein said arithmetic element controller of said arithmetic processor further comprises:

a branch register connected to said external bus for storing microprogram addresses used on uniconditional branch operations;

a branch and count register connected to said external data bus for storing microprogram addresses used on conditional branch operations;

said branch register containing a branch address field;

said branch and count register containing a count field, a reset field, and a branch address field;

said count field specifying the number of said conditional branch operations to be performed before transferring to the next process step;

said reset field specifying a reset value for the count to be reinitialized a plurality of times in a nested loop application;

a microprogram address register having an input connected to said branch register and said branch and count register for storing a branch address;

a microprogram storage having an address input connected to said microprogram address register for control and a data input connected to said storage controller for storing microprogram instructions for the operation of said arithmetic element and said working storage, accessible by said microprogram address;

whereby the execution of data conditional operations in said arithmetic element may proceed under the control of said arithmetic element controller.

38. The system of claim 22, wherein said arithmetic element controller further comprises:

a microprogram address register having an input connected to said external data bus;

a micro storage having an input connected to said storage controller;

a microinstruction register and decode logic having an input connected to said micro storage;

an address generation logic having an input connected to said microinstruction register and decode logic;

said address generation logic having an output connected to said working store;

said microinstruction register and decode logic having an output connected to said arithmetic unit;

a timing generator connected to said arithmetic unit and said working store;

said micro store having a cycle rate equal to the logic delay of one unit in the pipeline processor of said arithmetic unit;

a portion of each microinstruction issued from said micro storage to said microinstruction register and decode logic being used to control, on successive cycles, the operation of said pipeline processor in said arithmetic unit;

said working store having an accessing cycle which is an integral multiple of said unit of logic delay;

said microinstruction having a second portion controlling the address generation logic for accessing said working store once every said integral multiple of said unit of logic delay.

39. The system of claim 38, wherein said arithmetic element controller further comprises:

said working storage being divided into a left memory and a right memory with a memory address switching means controlling data flow into and out of said left memory and said right memory in response to a control signal generated by said address generation logic over a control line connecting said switching means to said address generation logic;

said arithmetic element controller controlling data transfer between the left half memory of said working store and sid arithmetic element when said right half memory of said working store is engaging in data transfers with said bulk storage, and vice versa.

40. A pipelined arithmetic processor, comprising:

an input connected to a working store;

a left multiplier register and a right multiplier register having inputs connected to said input line for receiving a first set of operands;

a two'"'"'s complement multiplier having a multiplier input connected to said first register and a multiplicand input connected to said right register for multiplying said first set of operands during a first time interval;

a left adder input register, a center adder input register, and a right adder input register, having an input connected to the product output of said multiplier;

said left adder input register and said center adder input register having a second input connected to said working store;

a scale factor register having a first input connected to an input control line and a second input connected to said working store;

a first prescaler having a data input connected to said left adder input register and a control input connected to said scale factor register;

a second prescaler having a data input connected to said center adder input register and a control input connected to said scale factor register;

a third prescaler having a data input connected to said right adder input register and a control input connected to said scale factor register;

a three input arithmetic logic unit having a first input connected to the output of said first prescaler, a second input connected to the output of said second prescaler, and a third input connected to the output of said third prescaler for adding the product of said first set of operands output from said multiplier to the input from said working store during a second time interval;

said multiplier multiplying a second set of operands during said second time interval;

a post scaler having a data input connected to the sum output of said arithmetic logic unit and a control input connected to said scale factor register;

a center adder output register and a right adder output register having inputs connected to the sum output of said arithmetic logic unit;

said post scaler having an output connected to a left adder output register which in turn has an output connected to said first prescaler;

said center adder output register having an output connected to said second prescaler and said right adder output register having an output connected to said third prescaler;

said post scaler having an output connected to a rounder which in turn has an output connected to an input of said left multiplier register and said right multiplier register;

an arithmetic element output register having an input connected to said rounder and an output connected to said working store for outputting the sum of the product of said first operands during a third time interval;

said arithmetic logic unit adding the product of said second set of operands output from said multiplier to the input from said working store during said third time interval;

said multiplier multiplying a third set of operands during said third time interval;

whereby the processor operates in a pipelined fashion at a staging rate such that new operands enter each stage of execution in the pipe in consecutive time intervals.