Computer input/output control apparatus

• US 4,041,473 A
• Filed: 05/12/1975
• Issued: 08/09/1977
• Est. Priority Date: 05/16/1974
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Bardotti, Angelo, Pederzini, Renzo
• Primary Examiner(s): Nusbaum, Mark E.
• Application Number:
  US05/576,523
• Time in Patent Office: 820 Days
• Field of Search: 340/172.5, 445/1
• US Class Current: 710/63
• CPC Class Codes: G06F 13/38 Information transfer, e.g. on bus G06F13/14 takes precedence

Abstract

Apparatus for the flexible coupling of peripheral units to a digital computer system, wherein any input/output port of the system is capable of communicating with a peripheral unit over various forms of interface.

Claims

1. In a digital computer system comprising a central processor, a first peripheral unit controlled by a peripheral control unit, and a second peripheral unit, the improved interface for providing for said central processor simultaneously to communicate with said peripheral control unit and to control directly and communicate with said second peripheral unit comprising:

first interface apparatus comprising a first universal port and a first module removably connectable to said first port and comprising a first circuit group and a first set of lines coupling said first circuit group to said peripheral control unit, said first circuit group for receiving control signals and data signals from said first port and from said peripheral control unit and in response to said signals received thereby transmitting appropriate and corresponding control and data signals to said first port and to said peripheral control unit; and

second interface apparatus comprising a second universal port and a second module removably connectable to said second port and comprising a second circuit group and a second set of lines coupling said second circuit group to said second peripheral unit, said second circuit group for receiving control signals and data signals from said second port and from said second peripheral unit and in response to said signals received thereby transmitting appropriate and corresponding control and data signals to said second port and to said second peripheral unit;

wherein said first circuit group includes first control means for responding to a first plurality of control signals received from said peripheral control unit and for transmitting a second plurality of control signals to said peripheral control unit, said second circuit group includes second control means for responding to a third plurality of control signals received from said second peripheral unit and for transmitting a fourth plurality of control signals to said second peripheral unit, said first and third pluralities being different in number and said second and fourth pluralities being different in number; and

said first control means transmits a subset of said second plurality of control signals in response to receipt of respective ones of a subset of said first plurality of control signals, said second control means transmits a subset of said fourth plurality of control signals in response to receipt of respective ones of a subset of said third plurality, said first and second circuit groups further including timing means for controlling the respective duration of said subset of said second plurality of signals to differ from the respective durations of said subset of said fourth plurality of signals, and for controlling the relative timing among the signals of said subset of said second plurality of signals to differ from the relative timing among said subset of said fourth plurality of signals; and

wherein said first and second universal ports are identical, each of said ports comprising an equal number of lines coupled to said central processor for transmitting control signals and data signals between said central processor and the one of said modules coupled to said port.

2. The interface of claim 1, wherein said second peripheral unit transmits over one of the lines of said second line set a first control signal operable in either one of first and second states, said first state denoting that said second peripheral unit is prepared to transfer information to the central processor, and wherein said second circuit group comprises:

a first register for storing a control information character representing the direction of information transfer over said second interface apparatus and the corresponding location of the source or destination of the information to be transferred;

a second register for storing information characters to be transferred to said second peripheral unit;

a third register for storing information characters received from said second peripheral unit;

a first flip-flop coupled to be responsive to said first control signal for generating a second control signal operable in either one of first and second states, said first state denoting that said second circuit group is prepared to transfer information to said second peripheral unit, said flip-flop responding to the transfer of said first control signal to the first state thereof for transferring said second control signal to the second state thereof and responding to the transfer of said first control signal to the second state thereof for transferring said second control signal to the first state thereof;

a second flip-flop for generating a third control signal for controlling the timing of the transfer of control information characters from said first register to said second peripheral unit; and

a third flip-flop for generating a fourth control signal for controlling the timing of the transfer of information characters which are not control information characters from said second register to said second peripheral unit.

3. The interface of claim 2 wherein said second circuit group further comprises a circuit for transferring a signal representing one bit of said control information character held in said first register to said second peripheral unit and, when an information transfer operation is to terminate, for transferring a signal representing the logical inverse of said one bit to said second peripheral unit.

4. In a data processing system having a plurality of different kinds of peripheral devices, the combination comprising:

a central processor provided with a plurality of universal ports for providing simultaneous communication with all of said peripheral devices, all of said ports being identical and comprising an equal number of lines and an identical first-type connector, all of the lines of each of said ports being coupled to a respective one of said first-type connectors, at least one group of said lines of each port transferring signals representing information characters between the respective connector and said central processor and others of said lines of each port transferring respective control signals between the respective connector and said central processor;

a first module for enabling communication and control via one of said ports between said central processor and a first kind of said peripheral devices, said first module comprising a first circuit group for receiving signals representing information characters and control signals from said central processor and said first-kind peripheral device and in response to said received signals transferring appropriate and corresponding signals representing information characters and control signals to said central processor and said first-kind peripheral device;

a second module for enabling communication and control via one of said ports between said central processor and a second kind of said peripheral devices, said second module comprising a second circuit group for receiving signals representing information characters and control signals from said central processor and said second-kind peripheral device and in response to said received signals transferring appropriate and corresponding signals representing information characters and control signals to said central processor and said second-kind peripheral device;

a first set of lines coupled between said first circuit group and said first-kind peripheral device for transferring signals representing information characters and control signals therebetween;

a second set of lines coupled between said second circuit group and said second-kind peripheral device for transferring signals representing information characters and control signals therebetween; and

a second-type connector connected to each of said modules and coupled to the respective circuit group of said module for enabling communication between said module and said central processor, each of said second-type connectors being removably matable with any one of said first-type connectors;

each of said second-type connectors being mated with one of said first-type connectors;

wherein said first and second sets of lines differ from each other in the number of lines and wherein said first circuit group includes first control means for responding to a first plurality of control signals received from said first-kind peripheral device and for transmitting a second plurality of control signals to said first-kind peripheral device, said second circuit group includes second control means for responding to a third plurality of control signals received from said second-kind peripheral device and for transmitting a fourth plurality of control signals to said second-kind peripheral device, said first and third pluralities being different in number and said second and fourth pluralities being different in number; and

said first control means transmits a subset of said second plurality of control signals in response to receipt of respective ones of a subset of said first plurality of control signals, said second control means tramsmits a subset of said fourth plurality of control signals in response to receipt of respective ones of a subset of said third plurality, said first and second circuit groups further including means for controlling the respective duration of said subset of said second plurality of signals to differ from the respective durations of said subset of said fourth plurality of signals, and for controlling the relative timing among the signals of said subset of said second plurality of signals to differ from the relative timing among said subset of said fourth plurality of signals.

5. The data processing system of claim 4, wherein:

said first circuit group comprises first and second registers for holding respective first-type and second-type information characters, said first-type information character representing (i) the direction information is to be subsequently transferred between said first circuit group and said first peripheral device and (ii) an information character storage location in said first-kind peripheral device with respect to which a second-type information character is to be inserted from said second register or is to be retrieved for transfer to said second register.

6. The data processing system of claim 5, wherein:

said second circuit group comprises a third register for holding all information characters to be transferred from said second kind peripheral device to said central processor.

7. The data processing system of claim 6, wherein:

said first circuit group further comprises control elements for transferring a first-type information character from the respective second-type connector to said first register and subsequently from said first-kind register to said first peripheral device prior to the transfer of any second-type information character between said second register and said first peripheral device, during any complete operation sequence.

8. The data processing system of claim 7, wherein:

said second circuit group further comprises control elements for transferring a third-type information character from second-kind peripheral device to said third register prior to the transfer of any other information character between said central processor and said second-kind peripheral device, during any complete operation sequence.

9. The data processing system of claim 8, wherein:

said third-type information character represents a particular type of information transfer operation to be carried out by the mutual interaction of said central processor and said second-kind peripheral device.

10. For employment with a central processor provided with a plurality of universal ports for providing simultaneous communication with a plurality of peripheral devices, all of said ports being identical and comprising an equal number of lines coupled to said central processor, and each of said ports comprising a first-type connector to which all of the lines of said port are connected, at least one group of said lines of each port transferring signals representing information characters and others of said lines of each port transferring individuals control signals;

the combination comprising;

a plurality of second-type connectors, each of said second-type connectors being removably matable with any one of said first-type connectors;

a first circuit group coupled to one of said second-type connectors;

a first set of lines coupling said first circuit group for communication with a first of said peripheral devices;

a second circuit group coupled to another of said second-type connectors; and

a second set of lines coupling said second circuit group for communication with a second of said peripheral devices;

each of said sets of lines transmitting between the respective ones of said circuit groups and said peripheral devices a plurality of control signals and a plurality of data signals, wherein said first and second line sets differ from each other in the number of lines and wherein said first circuit group includes first control means for responding to a first plurality of control signals received from said first peripheral device and for transmitting a second plurality of conrol signals to said first peripheral device, said second circuit group includes second control means for responding to a third plurality of control signals received from said second peripheral device and for transmitting a fourth plurality of control signals to said second peripheral device, said first and third pluralities being different in number and said second and fourth pluralities being different in number; and

said first control means transmits a subset of said second plurality of control signals in response to receipt of respective ones of a subset of said first plurality of control signals, said second control means transmits a subset of said fourth plurality of control signals in response to receipt of respective ones of a subset of said third plurality, said first and second circuit groups further including means for controlling the respective duration of said subset of said second plurality of signals to differ from the respective durations of said subset of said fourth plurality of signals, and for controlling the relative timing among the signals of said subset of said second plurality of signals to differ from the relative timing among said subset of said fourth plurality of signals;

wherein each of said second-type connectors is mated with one of said first-type connectors.