Integrated circuit and manufacture thereof

• US 4,041,522 A
• Filed: 08/19/1975
• Issued: 08/09/1977
• Est. Priority Date: 08/29/1974
• Status: Expired due to Term

• Current Assignee: Centre Electronique Horloger SA
• Original Assignee: Centre Electronique Horloger SA
• Inventors: Gerber, Bernard, Oguey, Henri J.
• Primary Examiner(s): Wojciechowicz, Edward J.
• Application Number:
  US05/605,845
• Time in Patent Office: 721 Days
• Field of Search: 357/23, 357/41, 357/42, 357/51, 357/59
• US Class Current: 257/377
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• CPC Class Codes: H01L 27/00 Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate details thereof H01L23/00, H01L29/00 - H10K10/00; assemblies consisting of a plurality of individual solid state devices H01L25/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03F 3/3001 with field-effect transistors
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 3/3545 Stabilisation of output, e.g. using crystal

Abstract

An integrated circuit comprises complementary FET having channels extending on the surface of a substrate and on the surface of a well in the substrate and gates formed in a layer of polycrystalline silicon insulated from the substrate and from each said well. A floating diode, i.e. connected neither to the substrate, nor to a well, is formed simultaneously with the FET by depositing and selectively etching a first doped oxide to cover a first region of the polycrystalline silicon, depositing an oppositely doped oxide over the remainder using the first oxide as mask, and oppositely doping the two regions of polycrystalline silicon by heat treatment. Alternatively, the second region can be doped by treatment in a gaseous phase or by ionic implantation, in either case using the first oxide as mask. Said regions are contiguous under the edge of the first doped oxide to form an autoaligned junction forming said floating diode which has a reverse conductivity notably greater than that of a junction in monocrystalline silicon, and easily reproduceable characteristics.

Claims

1. In an integrated circuit comprising complementary field effect transistors (FET) having channels extending on the surface of a substrate for one type of transistor and on the surface of a well in the substrate for the complementary type and gates formed in a layer of polycrystalline silicon insulated from the substrate and from each said well, and at least one so-called floating diode connected neither to the substrate nor to a said well, the improvement comprising a doped insulator covering a first region of said layer of polycrystalline silicon, the remainder of said layer of polycrystalline silicon forming a second oppositely-doped region, said two regions being contiguous at at least one location under an edge of said doped insulator to form an autoaligned junction forming said diode, said diode having a reverse conductivity notably greater than that of a junction in monocrystalline silicon, and having well-reproduceable characteristics.