Flat panel display device with integral thin film transistor control system
First Claim
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1. An electroluminescent display panel comprising;
- a. a planar substrate;
b. an array of spaced apart thin film transistor control circuitry disposed on the substrate;
c. an orthogonal matrix of rows and columns of switching signal, information signal, and power bus bars disposed on the substrate interconnecting and defining an array of unit display cells, each unit display cell including an individual thin film transistor control circuit;
d. a first electroluminescent electrode disposed on the substrate as part of each unit display cell and interconnected with the transistor control circuit;
e. a relatively thick laminated polymerized in place photoresist insulator layer disposed over the thin film transistor control circuitry and over interconnecting bus bars but not over the first electroluminescent electrodes;
f. a layer of electroluminescent material disposed over the entire area of the display panel over the insulator layer and in intimate contact with the individual first electroluminescent electrodes, which electroluminescent layer has a planar, smooth top surface;
g. a light transmissive common electrode deposited atop the electroluminescent layer and in intimate contact therewith.
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Abstract
A large area integrated solid-state flat panel display is detailed in which thin film transistor addressing and drive circuitry is provided at each individual picture point with a display medium. The preferred display medium is an electroluminescent phosphor layer. An insulating layer of laminated photoresist is disposed over all electrical circuit elements except the electroluminescent drive electrodes.
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Citations
4 Claims
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1. An electroluminescent display panel comprising;
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a. a planar substrate; b. an array of spaced apart thin film transistor control circuitry disposed on the substrate; c. an orthogonal matrix of rows and columns of switching signal, information signal, and power bus bars disposed on the substrate interconnecting and defining an array of unit display cells, each unit display cell including an individual thin film transistor control circuit; d. a first electroluminescent electrode disposed on the substrate as part of each unit display cell and interconnected with the transistor control circuit; e. a relatively thick laminated polymerized in place photoresist insulator layer disposed over the thin film transistor control circuitry and over interconnecting bus bars but not over the first electroluminescent electrodes; f. a layer of electroluminescent material disposed over the entire area of the display panel over the insulator layer and in intimate contact with the individual first electroluminescent electrodes, which electroluminescent layer has a planar, smooth top surface; g. a light transmissive common electrode deposited atop the electroluminescent layer and in intimate contact therewith. - View Dependent Claims (2, 3, 4)
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Specification
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Current AssigneeTownsend and Townsend and Crew LLP (Kilpatrick Townsend & Stockton LLP)
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Original AssigneeWestinghouse Electric Corporation (Paramount Global (f/k/a ViacomCBS Inc.))
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InventorsBrody, Thomas P., Luo, Fang-Chen
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Primary Examiner(s)LaRoche, Eugene R.
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Application NumberUS05/634,216Time in Patent Office634 DaysField of Search315/169 R, 315/169 TV, 315/51, 313/506, 313/509, 313/498, 313/502, 313/505, 340/166 ELUS Class Current313/505CPC Class CodesG09G 2300/0842 forming a memory circuit, e...G09G 3/32 semiconductive, e.g. using ...H04N 3/14 by means of electrically sc...
