Automatic tester for complex semiconductor components including combinations of logic, memory and analog devices and processes of testing thereof

• US 4,044,244 A
• Filed: 08/06/1976
• Issued: 08/23/1977
• Est. Priority Date: 08/06/1976
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Millham, Ernest H., Foreman, Steven H., Prilik, Ronald Jay, Ortloff, James E.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US05/712,303
• Time in Patent Office: 382 Days
• Field of Search: 235/153 AC, 235/153 R, 235/153 AK, 235/153 A, 235/150.5, 324/73 R, 324/73 AT, 340/172.5
• US Class Current: 714/724
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071

Abstract

Logic and analog functions in a complex semiconductor component are stuck fault and parametrically tested through an analog/digital measurement adapter coupled to logic and analog testers. Both logic and analog testers are under computer control whose purpose is to direct the testing sequence, log test results, perform algorithmic calculations on the data and diagnose failing devices in the component under test. The adapter provides the electrical environment to match a range of components under test to the logic and analog testers. The adapter is also under computer control to permit impedance matching of a multiplicity of digitally controlled stimulus/response units connected through a multiplexor to the range of components under test.

Claims

1. A testing apparatus for stimulating and measuring analog properties of a circuit under test while enabling the simultaneous stimulation and measurement by a logic testing apparatus on a plurality of terminals of the circuit under test, connected to the I/O bus of a central processing unit for receiving an instruction having an address and a data component, the address component including an analog/logic selection field, an instrument selection field, and a circuit under test pin selection field and the data portion including an instrument data field and a buffer circuit data field, comprising:

an instrument decoder having an input connected to said central processing unit I/O bus;

a first testing instrument having a control input connected to an output of said instrument decoder and a second testing instrument having a control input connected to an output of said instrument decoder, said first and second testing instruments having data lines connected to said central processing unit I/O bus;

said instrument decoder generating an enabling signal to said first testing instrument in response to the receipt of a first instrument select field in a first instruction output from said central processing unit, causing said first testing instrument to generate a signal waveform on an output line, characterized by a first instrument data field in said first instruction;

said instrument decoder enabling said second testing instrument in response to the receipt of a second instrument select field in a second instruction output from said central processing unit, causing said second testing instrument to measure a second signal waveform on an input line, based upon measurement criteria specified by a second instrument data field in said second instruction;

a multiplexor having a first signal input connected to the output of said first testing instrument and a control input for receiving a component under test pin select field from said first instruction;

a first buffer circuit having an input connected to a first output from said multiplexor, which first output is connected through said multiplexor to said signal output of said first test instrument in response to a component under test pin select field in said first instruction;

a buffer circuit decoder having an input connected to said I/O bus from said central processing unit and a control input connected to said first buffer circuit, for connecting said first output from said multiplexor, through said first buffer circuit to a first terminal on said component under test in response to a buffer circuit data field in said first instruction, enabling the input of said first signal waveform to said first terminal on said component under test;

a second buffer circuit having an input connected to a second terminal of said component under test, which second terminal generates said second signal waveform which is the component under test'"'"'s response to said first signal waveform;

a second buffer circuit decoder having an input connected to said I/O bus of said central processing unit and a control output connected to said second buffer circuit for connecting said second terminal of said component under test through said second buffer circuit to a second input line to said multiplexor in response to a second buffer circuit data field in said second instruction;

said multiplexor having a second output line connected to said signal input line for said second testing instrument, connected through said multiplexor to said second buffer circuit in response to a second circuit under test pin select field in said second instruction;

said second testing instrument measuring said second signal waveform generated from said second terminal of said component under test and generating a digital representation of said measurement which is output over said output line of said second testing instrument to the I/O bus of said central processing unit;

whereby a plurality of test may be performed on the component under test.

10. The apparatus of claim 1, wherein said digital representation of said measurement input to said central processing unit is stored with previously stored similar representations which are processed by arithmetic algorithms in said central processing unit to analyze the operational characteristics of said component under test.

13. The apparatus of claim 1, which further comprises:

a third buffer circuit having an input connected to said first terminal of said component under test, which first terminal receives said first signal waveform;

a terminating impedance, matched to the output impedance of said first test instrument;

whereby signal reflection losses are reduced.

14. The apparatus of claim 1, which further comprises:

a third buffer circuit having an input connected to said first terminal of said component under test, which first terminal receives said first signal waveform;

a third buffer circuit decoder having an input connected to said I/O bus of said central processing unit and a control output connected to said third buffer circuit for connecting said first terminal of said component under test through said third buffer circuit to a third input line to said multiplexor in response to a third buffer circuit data field in a third instruction;

said multiplexor having a third output line connected to a signal input line for a third testing instrument, connected through said multiplexor to said third buffer circuit in response to a third circuit under test pin selection field in said third instruction;

said third testing instrument monitoring said first signal waveform received at said first terminal of said component under test and generating a digital representation of said monitored first signal waveform which is output over the output line of said third testing instrument to the I/O bus of said central processing unit;

whereby feedback control of said first test instrument can be carried out.

15. The apparatus of claim 1, which further comprises:

a parametic testing unit having an output line for forcing a d.c. signal;

a parametric measuring unit having an input line for measuring said d.c. signal;

a third buffer circuit having an input connected to a third terminal of said component under test, which third terminal receives said d.c. signal;

a third buffer circuit decoder having an input connected to said I/O bus of said central processing unit and a control output connected to said third buffer circuit for connecting said third terminal of said component under test through said third buffer circuit to said output line of said parametric testing unit and for connecting said third terminal of said component under test to said input line of said parametric measurement unit, in response to a third buffer circuit data field in a third instruction;

whereby the d.c. parametric characteristics of said third terminal can be monitored.

2. The apparatus of claim 2 which further comprises:

a logic tester having an input connected to said I/O bus, a stimulus output line connected to said first buffer circuit and a measurement input line connected to said second buffer circuit, for selectively carrying out digital testing of said component under test in response to said analog/logic selection field in said first and second instruction;

whereby both digital and analog tests may be simultaneously carried out on the component under test.

3. The apparatus of claim 2, wherein said multiplexor further comprises:

a plurality of elementary crossbar multiplexors with stub cutoffs, each elementary multiplexor being selectively connected to adjacent elementary multiplexors when the associted crosspoint is not selected;

whereby spurious reflections from signal waveforms switched at a crosspoint, are reduced.

4. The apparatus of claim 2, wherein said buffer circuits further comprise:

an input/output analog line connected to said multiplexor, a logic detection output line connected to said multiplexor, a logic driver input line connected to said multiplexor, and an input/output line connected to a terminal on said component under test.

5. The apparatus of claim 4, wherein said buffer circuits further comprise:

a logic driver circuit having a first relay connected between said logic driver input line and said component under test input/output line, a second relay in series with a diode poled with its cathode towards said logic driver input line, connected between said logic driver input line and said component under test input/output line and a third relay in series with a second diode having its anode poled toward said logic driver input line, connected between said logic driver input line and said component under test input/output line;

whereby logic drivers in said logic tester can be selectively connected to a terminal on said component under test.

6. The apparatus of claim 5, wherein said buffer circuit further comprises:

a programmable current source selectively connected between said component under test input/output line and the first plate of a capacitor whose second plate is connected to ground, for selectively reverse biasing said first or second diodes, thereby isolating said terminal of said component under test from the capacitance of said logic driver input line.

7. The apparatus of claim 6, wherein said buffer circuit further comprises:

a fourth relay which selectively connects said component under test to said input/output analog line whereby analog circuit testing of said component under test may be carried out.

8. The apparatus of claim 7, wherein said buffer circuit further comprises:

a fifth relay having a buffer amplifier in series therewith connected between said input/output line of said component under test and said analog input/output line;

whereby response signals generated by said component under test may be buffered prior to measurement by said second testing instrument.

9. The apparatus of claim 8, wherein said buffer circuit decoder further comprises:

a read only storage array having an address input for receiving said buffer circuit data field and a plurality of data output signal lines connected to selected combinations of said first, second, third, fourth and fifth relays;

whereby said first, second, third, fourth and fifth relays may be selectively closed in response to said buffer circuit data field.

11. The apparatus of claim 8, wherein said buffer amplifier output impedance matches the input impedance of said signal input line for said second testing instrument.

12. The apparatus of claim 11, wherein the input impedance of said buffer amplifier is selectively adjustable.

16. The apparatus of claim 8, wherein the input of said buffer amplifier has a selectable signal attenuator.