Dynamic type semiconductor memory device

• US 4,044,342 A
• Filed: 04/22/1976
• Issued: 08/23/1977
• Est. Priority Date: 04/22/1975
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Electric Co., Ltd.
• Original Assignee: Tokyo Shibaura Electric Co., Ltd.
• Inventors: Suzuki, Yasoji, Ochii, Kiyofumi
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US05/679,177
• Time in Patent Office: 488 Days
• Field of Search: 340/173 R, 340/173 FF, 340/173 CA, 340/173 DR, 307/238, 307/279
• US Class Current: 365/222
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

The dynamic type semiconductor memory device comprises a refresh circuit and a plurality of memory cells which are connected between a data input line and a data output line, a plurality of read/write command signal lines and a plurality of word selection lines provided for respective semiconductor memory cells. Each semiconductor memory cell comprises serially connected first p-channel MOS transistor and a second n-channel MOS transistor having gate electrodes connected to the read/write command signal line and the data input line respectively, a third p-channel MOS transistor connected between the data output line and the word selection line and having a gate electrode connected to the node between the first and second transistors, and a parasitic capacitance connected to the node between the first and second transistors for storing data.

Claims

1. A dynamic type semiconductor memory device comprising a refresh circuit, a plurality of semiconductor memory cells which are connected across a data input line and a data output line, a plurality of read/write command signal line and a plurality of word selection lines which are provided for each of said semiconductor memory cells, each of said semiconductor memory cells comprises serially connected first and second transistors of the opposite polarity, the gate electrodes of said first and second transistors being connected to said read/write command signal line and said data input line, respectively, a third transistor connected across said data output line and said word selection line, the gate electrode of said third transistor being connected to the node between said first and second transistors, and a parasitic capacitance formed at the common node between said first, second and third transistors for storing data.

2. A dynamic type semiconductor memory device comprising a refresh circuit connected across a data input line and a data output line;

a plurality of semiconductor memory cells connected across said data input line and said data output line;

a plurality of read/write command signal lines and a plurality of word selection lines for respective semiconductor memory cells; and

address gate circuit connected across said data input line and said data output line;

each of said semiconductor memory cells comprising serially connected first and second transistors of the opposite polarity, the gate electrodes of said first and second transistors being connected to said read/write command signal line and said data input line respectively, a third transistors connected across the data output line and said word selection line and having a gate electrode connected to the node between said first and second transistors, and a parasitic capacitance formed at the common node between said first, second and third transistors for storing data.

3. The dynamic type semiconductor memory device according to claim 2 wherein said address gate circuit comprises a p-channel MOS transistor connected between said data output line a point charged at a first potential and an n-channel MOS transistor connected between said data input line and a point charged at a second potential, said first and second transistors of said semiconductor memory cells are constituted by a p-channel MOS transistor and an n-channel MOS transistor respectively, and said third transistor comprises an n-channel MOS transistor.

4. The dynamic type semiconductor memory device according to claim 2 wherein said address gate circuit comprises a p-channel MOS transistor connected between said data input line and a point charged at a first potential and an n-channel MOS transistor connected between said data output line and a point charged at a second potential, said first and second transistors of said semiconductor memory cells are constituted by a p-channel MOS transistor and an n-channel MOS transistor respectively, and said third transistor comprises a p-channel MOS transistor.

5. A dynamic type semiconductor memory device comprising a refresh circuit, a plurality of semiconductor memory cells, and an address gate circuit which are respectively connected across a data input line and a data output line, and a plurality of read/write command signal lines and a plurality of word selection lines which are provided for respective semiconductor memory cells, each of said semiconductor memory cells comprising serially connected first and second transistors of the opposite polarity, the gate electrodes of said first and second transistors being connected to said read/write command signal line and said data input line respectively, third and fourth transistors which are connected in series between said data output line and a point charged at a definite potential, the gate electrodes of said third and fourth transistors being connected to the node between said first and second transistors and said word selection line respectively, and a parasitic capacitance formed at the node between said first and second transistors for storing data.

6. The dynamic type semiconductor memory device according to claim 5 wherein said address gate circuit comprises an n-channel MOS transistor connected between said data input line and a point charged at a second potential and a p-channel transistor connected between said data output line and a point charged at a first potential, the first and second transistors of said semiconductor cells are constituted by a p-channel MOS transistor and an n-channel MOS transistor respectively, and said third and fourth transistors of said semiconductor memory cells are constituted by n-channel MOS transistors respectively.

7. The dynamic type semiconductor memory device according to claim 5 wherein said address gate circuit comprises a p-channel MOS transistor connected between said data input line and a point charged at a first potential, and an n-channel MOS transistor connected between said data output line and a point charged at a second potential, said first and second transistors of said semiconductor memory cells comprise a p-channel MOS transistor and an n-channel MOS transistor respectively, said third and fourth transistors of said memory cells are constituted by p-channel MOS transistors respectively.

8. A dynamic type semiconductor memory device comprising a refresh circuit connected between a data input line and a data output line;

a plurality of semiconductor memory cells connected between said data input and output lines;

a plurality of read/write command signal lines and a plurality of word selection lines provided for respective semiconductor memory cells; and

an address gate circuit connected between said data input line and said data output line;

each of said semiconductor memory cells comprises serially connected first and second transistors of the opposite polarity the gate electrodes of which are connected to said data input line and said read/write command signal line respectively, a third transistor connected between said data output line and said word selection line, the gate electrode of said third transistor being connected to the node between said first and second transistors, and a parasitic capacitance connected to the common node between said first, second and third transistor for storing data.

9. The dynamic type semiconductor memory device according to claim 8 wherein said address gate circuit comprises a p-channel MOS transistor connected between said data output line and a point charged at a first potential, and an n-channel MOS transistor connected between said data input line and a point charged at a second potential, the first and second transistors of said semiconductor memory cell are constituted by a p-channel MOS transistor and an n-channel MOS transistor respectively, and said third transistor of said semiconductor memory cell is constituted by an n-channel MOS transistor.

10. The dynamic type semiconductor memory device according to claim 8 wherein said address gate circuit comprises a p-channel MOS transistor connected between said data input line and a point charged at a first potential, and an n-channel MOS transistor connected between said data output conductor and a point charged at a second potential, the first and second transistors of said semiconductor memory cells are constituted by a p-channel MOS transistor and an n-channel MOS transistor respectively, and the third transistor of said semiconductor memory cell is constituted by a p-channel MOS transistor.

11. A dynamic type semiconductor memory device comprising a refresh circuit, a plurality of semiconductor memory cells and an address gate circuit which are connected between a data input line and a data output line, a plurality of read/write command signal lines, and a plurality of word selection lines, said read/write command signal lines and word selection lines provided for respective semiconductor memory cells, each of said semiconductor memory cells comprising serially connected first and second transistors of the opposite polarity, the gate electrodes of said first and second transistors being connected to said data input line and said read/write command signal line respectively, third and fourth transistors which are connected in series between said data output line and a point charged at a predetermined potential, the gate electrodes of said third and fourth transistors being connected to the node between said first and second transistors and said word selection line respectively, and a parasitic capacitance formed at the node between said first and second transistors for storing data.

12. The dynamic type semiconductor memory device according to claim 11 wherein said address gate circuit comprises a p-channel transistor connected between said data output line and a point charged at a first potential, an n-channel MOS transistor connected between said data input line and a point charged at a second potential, the first and second transistors of said semiconductor memory cells are constituted by a p-channel MOS transistor and an n-channel MOS transistor respectively, and the third and fourth transistors of said semiconductor memory cells are constituted by n-channel MOS transistors respectively.

13. The dynamic type semiconductor memory device according to claim 11 wherein said address gate circuit comprises a p-channel MOS transistor connected between said data input line and a point charged at a first potential, and an n-channel MOS transistor connected between said data output line and a point charged at a second potential, the first and second transistors of said semiconductor memory cells are constituted by a p-channel MOS transistor and an n-channel MOS transistor respectively, and the third and fourth transistors of said semiconductor memory cells are constituted by p-channel MOS transistors respectively.