MOS one transistor cell RAM having divided and balanced bit lines, coupled by regenerative flip-flop sense amplifiers, and balanced access circuitry
First Claim
1. A dynamic MOS memory having a plurality of storage elements arranged;
- as a matrix, in rows and columns, each of said storage elements comprising a MOS transistor connected in series with a storage capacitor means said memory further comprising;
a. a balanced data access circuit for reading the binary status of, or writing a binary signal in, any selected storage element, said access circuit having first and second complementary data terminals;
b. a balanced data access bus, having first and second complementary data bus lines, the first and second complementary data bus lines being respectively connected to the first and second complementary data terminals of the balanced data access circuit;
c. a plurality of regenerative flip-flop balanced sense amplifiers, each of said sense amplifiers having first and second input/output nodes;
d. a plurality of bit lines, each bit line being divided into a first and a second part, the MOS transistors of the storage elements corresponding to any one bit line being connected in substantially equal number to the first and second parts of said any one bit line, the first and second parts of any one bit line, being respectively connected to the first and second input/output nodes of the regenerative flip-flop balanced sense amplifier corresponding to said any one bit line, and extending, adjacent each other, from said sense amplifier to the balanced data access bus for respective connection through a first and a second MOS access transistor to the first and second complementary data bus lines;
whereby, by turning ON the first and second MOS access transistors corresponding to a particular bit line, a substantially electrically balanced path is established from the first and second input/output nodes of the regenerative flip-flop balanced sense amplifier corresponding to said particular bit line to the first and second complementary data terminals of the balanced data access circuit.
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Accused Products
Abstract
A dynamic MOS one transistor cell memory having a plurality of divided bit lines and a corresponding plurality of flip-flop sense amplifiers. Each bit line being divided into two electrically balanced parts which run adjacent and parallel to each other, and extend from the input/output nodes of their corresponding flip-flop sense amplifier to a balanced data access bus. The balanced data access bus being connected, in turn, to balanced data access, or read/write, circuitry. By virtue of the connection of balanced bit, and bus lines, and balanced data access circuitry, to each flip-flop sense amplifier, the probability of reading errors due to circuit imbalances at the input/output nodes of the flip-flops is greatly lessened. The direct connection, from the read/write circuitry to both parts of each bit line, arising from this arrangement obviates the need to enable a flip-flop sense amplifier in order to perform a writing operation, and permits a read-modify-write operation with flip-flop sense amplifiers designed with dynamic loads.
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Citations
10 Claims
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1. A dynamic MOS memory having a plurality of storage elements arranged;
- as a matrix, in rows and columns, each of said storage elements comprising a MOS transistor connected in series with a storage capacitor means said memory further comprising;
a. a balanced data access circuit for reading the binary status of, or writing a binary signal in, any selected storage element, said access circuit having first and second complementary data terminals; b. a balanced data access bus, having first and second complementary data bus lines, the first and second complementary data bus lines being respectively connected to the first and second complementary data terminals of the balanced data access circuit; c. a plurality of regenerative flip-flop balanced sense amplifiers, each of said sense amplifiers having first and second input/output nodes; d. a plurality of bit lines, each bit line being divided into a first and a second part, the MOS transistors of the storage elements corresponding to any one bit line being connected in substantially equal number to the first and second parts of said any one bit line, the first and second parts of any one bit line, being respectively connected to the first and second input/output nodes of the regenerative flip-flop balanced sense amplifier corresponding to said any one bit line, and extending, adjacent each other, from said sense amplifier to the balanced data access bus for respective connection through a first and a second MOS access transistor to the first and second complementary data bus lines; whereby, by turning ON the first and second MOS access transistors corresponding to a particular bit line, a substantially electrically balanced path is established from the first and second input/output nodes of the regenerative flip-flop balanced sense amplifier corresponding to said particular bit line to the first and second complementary data terminals of the balanced data access circuit. - View Dependent Claims (2, 3, 5)
- as a matrix, in rows and columns, each of said storage elements comprising a MOS transistor connected in series with a storage capacitor means said memory further comprising;
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4. A dynamic MOS memory having a plurality of storage elements arranged, as a matrix, in rows and columns, each of said storage elements comprising a MOS transistor connected in series with a storage capacitor means, said memory further comprising:
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a. a word selection means having a plurality of word selection lines, any one word selection line being connected to the gate electrodes of the MOS transistors of a group of storage elements in a particular row of storage elements associated with a particular word; b. a balanced data access circuit for reading the binary status of, or writing a binary signal in, any selected storage element, said access circuit having first and second complementary data terminals; c. a balanced data access bus, having first and second complementary data bus lines, the first and second complementary data bus lines being respectively connected to the first and second complementary data terminals of the balanced data access circuit; d. a plurality of regenerative flip-flop balanced sense amplifiers;
each of said sense amplifiers having first and second input/output nodes and first and second MOS transistors, the gate electrodes of the first and second MOS transistors being respectively connected to the second and first input/output nodes, one electrode of the source and drain electrodes of the first MOS transistor being connected to a corresponding one electrode of the source and drain electrodes of the second MOS transistor, the other electrode of the source and drain electrodes of the first MOS transistor being connected to the first input/output node while the other electrode of the source and drain electrodes of the second MOS transistor being connected to the second input/output node;e. a plurality of bit lines, each bit line being divided into a first and second part, the MOS transistors of the storage elements corresponding to any one bit line being connected in substantially equal number to the first and second parts of said any one bit line, the first and second parts of said any one bit line being respectively connected to the first and second input/output nodes of the regenerative flip-flop balanced sense amplifier corresponding to said any one bit line, and extending, adjacent each other, from said sense amplifier to the balanced data access bus for respective connection through a first and a second MOS access transistor to the first and second complementary data bus lines; f. bit decoder means having a plurality of bit decoder lines, any one bit decoder line corresponding to a particular bit line and being connected to the gate electrodes of the first and second MOS access transistors respectively linking the first and second parts of said particular bit line to the first and second complementary bus lines; whereby, during a writing operation, the first and second MOS access transistors of a selected bit line are turned ON by a signal from the bit decoder means, such that complementary binary signals generated by said access circuit are transmitted via said data bus lines through said MOS access transistors to the first and second parts of said selected bit line and thereafter to the storage capacitor means of the storage element connected to one part of said selected bit line by a signal from the word selection means; and whereby, during a reading operation, complementary binary signals are generated at the first and second input/output nodes of the regenerative flip-flop sense amplifier corresponding to a selected bit line, in response to the binary state of a storage element connected to said selected bit line, said complementary binary signals being transmitted by the balanced data access bus to the balanced data access circuit by turning ON the first and second MOS access transistors corresponding to said selected bit line. - View Dependent Claims (6, 7, 8, 9, 10)
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Specification