MOS one transistor cell RAM having divided and balanced bit lines, coupled by regenerative flip-flop sense amplifiers, and balanced access circuitry

• US 4,045,783 A
• Filed: 04/12/1976
• Issued: 08/30/1977
• Est. Priority Date: 04/12/1976
• Status: Expired due to Term

• Current Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Original Assignee: Standard Microsystems Corporation (Microchip Technology Incorporated)
• Inventors: Harland, Robert Francis
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US05/676,066
• Time in Patent Office: 505 Days
• Field of Search: 340/173 R, 340/173 CA, 340/173 FF, 307/238, 307/279
• US Class Current: 365/202
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

A dynamic MOS one transistor cell memory having a plurality of divided bit lines and a corresponding plurality of flip-flop sense amplifiers. Each bit line being divided into two electrically balanced parts which run adjacent and parallel to each other, and extend from the input/output nodes of their corresponding flip-flop sense amplifier to a balanced data access bus. The balanced data access bus being connected, in turn, to balanced data access, or read/write, circuitry. By virtue of the connection of balanced bit, and bus lines, and balanced data access circuitry, to each flip-flop sense amplifier, the probability of reading errors due to circuit imbalances at the input/output nodes of the flip-flops is greatly lessened. The direct connection, from the read/write circuitry to both parts of each bit line, arising from this arrangement obviates the need to enable a flip-flop sense amplifier in order to perform a writing operation, and permits a read-modify-write operation with flip-flop sense amplifiers designed with dynamic loads.

Claims

1. A dynamic MOS memory having a plurality of storage elements arranged;

as a matrix, in rows and columns, each of said storage elements comprising a MOS transistor connected in series with a storage capacitor means said memory further comprising;

a. a balanced data access circuit for reading the binary status of, or writing a binary signal in, any selected storage element, said access circuit having first and second complementary data terminals;

b. a balanced data access bus, having first and second complementary data bus lines, the first and second complementary data bus lines being respectively connected to the first and second complementary data terminals of the balanced data access circuit;

c. a plurality of regenerative flip-flop balanced sense amplifiers, each of said sense amplifiers having first and second input/output nodes;

d. a plurality of bit lines, each bit line being divided into a first and a second part, the MOS transistors of the storage elements corresponding to any one bit line being connected in substantially equal number to the first and second parts of said any one bit line, the first and second parts of any one bit line, being respectively connected to the first and second input/output nodes of the regenerative flip-flop balanced sense amplifier corresponding to said any one bit line, and extending, adjacent each other, from said sense amplifier to the balanced data access bus for respective connection through a first and a second MOS access transistor to the first and second complementary data bus lines;

whereby, by turning ON the first and second MOS access transistors corresponding to a particular bit line, a substantially electrically balanced path is established from the first and second input/output nodes of the regenerative flip-flop balanced sense amplifier corresponding to said particular bit line to the first and second complementary data terminals of the balanced data access circuit.

2. The dynamic MOS memory as defined in claim 1 further comprising a word selection means having a plurality of word selection lines, any one word selection line being connected to the gate electrodes of the MOS transistors of a group of storage elements in a particular row of storage elements associated with a particular word;

whereby the storage capacitor means of the storage elements associated with said particular word are connected to, or disconnected from, their corresponding bit lines by turning ON or OFF said MOS transistors under control of said word selection means.

3. The dynamic MOS memory as defined in claim 2 further comprising a bit decoder means having a plurality of bit decoder lines, any one bit decoder line corresponding to a particular bit line and being connected to the gate electrodes of the first and second MOS access transistors respectively linking the first and second parts of said particular bit line to the first and second complementary bus lines;

whereby during a reading operation, complementary binary signals, present on the first and second parts of said particular bit line, are applied to the first and second complementary data terminals of the balanced data access circuit by turning ON said first and second MOS access transistors and whereby, during a writing operation, complementary binary signals generated by said access circuit are carried by said bus lines and the first and second parts of said bit line to the storage capacitor means of the storage element selected for the writing operation.

5. The dynamic MOS memory as defined in claim 1 wherein the regenerative flip-flop balanced sense amplifiers are characterized by dynamic load circuitry, each flip-flop balanced sense amplifier having first and second MOS load transistors arranged for connection to a supply potential, said first and second MOS load transistors being respectively connected through third and fourth MOS transistors to the first and second input/output nodes of said sense amplifier, the conduction of said third and fourth MOS transistors being controlled by means responsive to the relative potentials of the first and second parts of the corresponding divided bit line so as to interrupt the flow of current in the MOS load transistor connected to the input/output node of said sense amplifier having the lower relative potential.

4. A dynamic MOS memory having a plurality of storage elements arranged, as a matrix, in rows and columns, each of said storage elements comprising a MOS transistor connected in series with a storage capacitor means, said memory further comprising:

a. a word selection means having a plurality of word selection lines, any one word selection line being connected to the gate electrodes of the MOS transistors of a group of storage elements in a particular row of storage elements associated with a particular word;

b. a balanced data access circuit for reading the binary status of, or writing a binary signal in, any selected storage element, said access circuit having first and second complementary data terminals;

c. a balanced data access bus, having first and second complementary data bus lines, the first and second complementary data bus lines being respectively connected to the first and second complementary data terminals of the balanced data access circuit;

d. a plurality of regenerative flip-flop balanced sense amplifiers;

each of said sense amplifiers having first and second input/output nodes and first and second MOS transistors, the gate electrodes of the first and second MOS transistors being respectively connected to the second and first input/output nodes, one electrode of the source and drain electrodes of the first MOS transistor being connected to a corresponding one electrode of the source and drain electrodes of the second MOS transistor, the other electrode of the source and drain electrodes of the first MOS transistor being connected to the first input/output node while the other electrode of the source and drain electrodes of the second MOS transistor being connected to the second input/output node;

e. a plurality of bit lines, each bit line being divided into a first and second part, the MOS transistors of the storage elements corresponding to any one bit line being connected in substantially equal number to the first and second parts of said any one bit line, the first and second parts of said any one bit line being respectively connected to the first and second input/output nodes of the regenerative flip-flop balanced sense amplifier corresponding to said any one bit line, and extending, adjacent each other, from said sense amplifier to the balanced data access bus for respective connection through a first and a second MOS access transistor to the first and second complementary data bus lines;

f. bit decoder means having a plurality of bit decoder lines, any one bit decoder line corresponding to a particular bit line and being connected to the gate electrodes of the first and second MOS access transistors respectively linking the first and second parts of said particular bit line to the first and second complementary bus lines;

whereby, during a writing operation, the first and second MOS access transistors of a selected bit line are turned ON by a signal from the bit decoder means, such that complementary binary signals generated by said access circuit are transmitted via said data bus lines through said MOS access transistors to the first and second parts of said selected bit line and thereafter to the storage capacitor means of the storage element connected to one part of said selected bit line by a signal from the word selection means;

and whereby, during a reading operation, complementary binary signals are generated at the first and second input/output nodes of the regenerative flip-flop sense amplifier corresponding to a selected bit line, in response to the binary state of a storage element connected to said selected bit line, said complementary binary signals being transmitted by the balanced data access bus to the balanced data access circuit by turning ON the first and second MOS access transistors corresponding to said selected bit line.

6. The dynamic MOS memory as defined in claim 4 wherein the regenerative flip-flop balanced sense amplifiers are characterized by dynamic load circuitry, each flip-flop balanced sense amplifier having first and second MOS load transistors arranged for connection to a supply potential, said first and second MOS load transistors being respectively connected through third and fourth MOS transistors to the first and second input/output nodes of said sense amplifier, the conduction of said third and fourth MOS transistors being controlled by means responsive to the relative potentials of the first and second parts of the corresponding divided bit line so as to interrupt the flow of current in the MOS load transistor connected to the input/output node of said sense amplifier having the lower relative potential.

7. The dynamic MOS memory as defined in claim 4 wherein each word selection line crosses the first and second parts of each bit line;

whereby electrical signals on any word selection line affect the first and second parts of each bit line in a balanced manner.

8. The dynamic MOS memory as defined in claim 4 wherein the first and second MOS access transistors corresponding to any one bit line have matched electrical parameters;

whereby, upon application of a signal to the gate electrodes of said first and second MOS access transistors by the bit decoder means, electrically balanced signals are coupled to the first and second parts of said bit line by feed-through from the gate electrodes of said first and second MOS access transistors to the first and second parts of said bit line.

9. The dynamic MOS memory as defined in claim 4 wherein the data bus lines and the bit lines are formed of metal, and wherein the word selection lines are formed of polysilicon material.

10. The dynamic MOS memory as defined in claim 6 wherein the means responsive to the relative potentials of the first and second parts of said bit line comprises;

ninth, seventh, eighth and tenth MOS transistors associated with each particular bit line and sequentially connected to form a series circuit from the first to the second parts of said particular bit line;

the junction of the ninth and seventh MOS transistors being connected to the gate electrode of the third MOS transistor, the junction of the seventh and eighth MOS transistors being arranged for connection to a supply potential, and the junction of the eighth and tenth MOS transistors being connected to the gate electrode of the fourth MOS transistor;

the gate electrodes of the seventh and eighth MOS transistors being interconnected and arranged for connection to an enable signal; and

the gate electrodes of the ninth and tenth MOS transistors being respectively connected to the second and first parts of said particular bit line.