Fault-tolerant cell addressable array
First Claim
1. A defect-tolerant cell addressable array comprising:
- a. an array of functional cells arranged in rows and columns;
b. a plurality of redundant functional cells;
c. cell selection means responsive to cell address code signals for selectively addressing an individual functional cell in a respective row and column and simultaneously addressing a corresponding redundant cell;
d. memory means in which address codes of the row and column addresses of defective functional cells are selectively storable, said memory means being responsive to said cell address code signals for detecting when the cell address code signals correspond to the address codes of defective ones of said functional cells and for generating a signal indicative thereof; and
e. logic means responsive to the signal generated by said memory means for directing data into and/or out of the respectively addressed redundant cell instead of an addressed defective cell.
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Accused Products
Abstract
A small programmable memory means such as an electrically programmable logic array is incorporated on the chip of a conventional bit addressable random access memory or other cell addressable array circuit. The array has one or more superfluous rows and/or columns of cells held in reserve. Processing and testing of the chip is conducted in a conventional manner. Chips with faulty cells are corrected by programming the memory means with the cell addresses of the faulty cell locations. Subsequently, the memory means will respond to any of these addresses and, through interaction with input/output logic, cause the data input and/or output to be steered to or from a reserve cell instead of the addressed faulty cell.
61 Citations
53 Claims
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1. A defect-tolerant cell addressable array comprising:
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a. an array of functional cells arranged in rows and columns; b. a plurality of redundant functional cells; c. cell selection means responsive to cell address code signals for selectively addressing an individual functional cell in a respective row and column and simultaneously addressing a corresponding redundant cell; d. memory means in which address codes of the row and column addresses of defective functional cells are selectively storable, said memory means being responsive to said cell address code signals for detecting when the cell address code signals correspond to the address codes of defective ones of said functional cells and for generating a signal indicative thereof; and e. logic means responsive to the signal generated by said memory means for directing data into and/or out of the respectively addressed redundant cell instead of an addressed defective cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A defect-tolerant cell addressable array comprising:
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a. an array of functional cells arranged in rows and columns; b. at least one redundant row or column of functional cells; c. cell selection means responsive to row and column address code signals for selectively addressing an individual cell in a respective row and column and for simultaneously addressing a corresponding cell in said at least one redundant row or column; d. programmable or programmed memory means coupled to receive said row and column address code signals for detecting the address codes of defective ones of said functional cells and generating a signal indicative thereof, said memory means including means for storing the row and column address codes of one or more defective cells of said array of functional cells; and e. logic means coupled to said memory means and responsive to the generated signal for selectively transferring data into and/or out of the addressed cell in said redundant row or column each time a defective cell is detected by said memory means and for otherwise selectively transferring data into and/or out of the addressed cell of said array. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A system of defect-tolerant cell addressable arrays comprising:
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a. a plurality of arrays of functional cells each being arranged in rows and columns; b. at least one redundant row or column of functional cells associated with each of said arrays; c. cell selection means responsive to row, column and array address code signals for selectively addressing an individual cell in a respective row, column and array and for simultaneously addressing a corresponding cell in the redundant row or column of such array; d. programmable or programmed memory means coupled to receive said row, column and array address code signals for detecting the address codes of defective ones of said functional cells and for generating a signal indicative thereof, said memory means including means for storing the row, column and array address codes of one or more defective cells of said arrays of functional cells; and e. logic means coupled to said memory means and responsive to the generated signal for selectively directing data into and/or out of the addressed cell of said arrays or said redundant row or column in dependence upon the signal generated by said memory means. - View Dependent Claims (47, 48, 49)
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50. A system of defect-tolerant cell addressable arrays comprising:
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a. a plurality of arrays, including at least one redundant array, of functional cells each being arranged in rows and columns; b. at least one redundant row or column of functional cells associated with each of said arrays; c. cell selection means responsive to row, column and array address code signals for selectively addressing an individual cell in a respective row, column and array; d. programmable or programmed memory means coupled to receive said row, column and array address code signals for detecting the address codes of defective ones of said functional cells and for generating a signal indicative thereof, said memory means including means for storing the row, column and array address codes of one or more defective cells of said arrays of functional cells; and e. logic means coupled to said memory means and responsive to said generated signal for directing data into and/or out of a functional cell in said redundant array instead of the defective cell in the addressed array. - View Dependent Claims (51)
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- 52. The system according to claim 59 wherein said plurality of arrays are integrated as a monolithic semiconductor structure.
Specification