Diagnostic testing apparatus and method

• US 4,048,481 A
• Filed: 12/17/1974
• Issued: 09/13/1977
• Est. Priority Date: 12/17/1974
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Barlow, George J., Bailey, Myrl Kennedy Jr.
• Primary Examiner(s): Atkinson, Charles E.
• Application Number:
  US05/533,743
• Time in Patent Office: 1,001 Days
• Field of Search: 235/153 AK, 235/153 AC, 340/172.5, 445/1
• US Class Current: 714/41
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units

Abstract

A microprogrammable peripheral controller in addition to being operative to controlling plurality of input/output devices in response to commands for processing information signals from a magnetic medium also includes apparatus for independently establishing a minimum operating capability within the controller. The apparatus includes a read-only control store arranged to store microinstructions and a limited number of basic bit patterns. The apparatus in response to an external control signal is operative to condition the data recovery apparatus included in the controller to receive the blocks of synchronization and data patterns arranged in a predetermined format and generated from basic bit patterns obtained from the control store. Simultaneously therewith, the apparatus inhibits normal transfer of information from the magnetic medium. Additionally, a plurality of record error indicator circuits included in the data recovery apparatus are operative to be switched during the processing of each of the blocks of bit patterns transferred through the recovery apparatus. The apparatus further includes comparison circuits which compare the state of the record error indicators with a predicted bit pattern for detecting whether the recovery apparatus is operating properly in processing the block of bit patterns transferred thereto. The states of other indicator storage circuits are modified to signals indicative of conditions occurring during the transfer of the generated bit patterns. The comparison circuits also compare the states of these circuits with a predicted bit pattern as further verification of recovery apparatus operation.

Claims

1. An improved input/output magnetic tape controller having microprogrammed processing means and data recovery means for assembling into bytes for transfer to a data processing system, digital signals received from a magnetic tape device obtained by reading signals arranged in a predetermined block format and recorded on a multichannel magnetic medium, said recovery means including a plurality of registers for deskewing said digital signals and assembling them into bytes, correction circuits coupled to different ones of said registers for correcting errors detected during said deskewing, a plurality of checking circuits coupled to different ones of said registers for detecting different types of error conditions occurring during said deskewing and assembling of said digital signals and a plurality of error indicator circuits coupled to said checking circuits, said controller further comprising:

a control store having a plurality of resident basic logic test routines, one of said routines for verifying the operation of said data recovery means, said one routine including a plurality of constants representative of initial patterns and expected result patterns;

decoder means for generating control signals in response to decoding microinstructions of said resident basic logic test routines;

selector circuit means coupled to said processing unit to said magnetic tape device and to a first one of said plurality of registers, said selector circuit means being operatively connected to apply selectively digital signals received from said device and said processing means to said first one of said plurality of registers; and

,

means coupling said plurality of error indicator circuits to said processing means;

said decoder means being conditioned by microinstructions of said one routine to generate signals for conditioning said selector circuit means to couple said first one of said registers to said processing means inhibiting transfer of said digital signals from said device, other microinstructions of said one routine conditioning said decoder means to generate signals for conditioning said processing means to generate digital signals of a first block from said initial patterns arranged in said predetermined format and said decoder means being conditioned by a sequence of test microinstructions at the completion of said recovery unit having assembled all of said digital signals of said first block into bytes to compare the states of said error indicator circuits with one of said expected result patterns for verifying that said recovery unit is operating properly.

2. A peripheral system including a microprogrammed processing apparatus coupled to a data processing system and to at least one magnetic tape peripheral device for reading and recording on a multichannel magnetic medium successive bytes of digital signals in blocks, each block having a predetermined format, sad microprogrammed processing apparatus comprising:

an addressable control store for storing microprograms used to perform said reading and recording of said bytes of digital signals, said store including addressing means and a plurality of storage locations for storing a plurality of basic test routines including a recovery routine for verifying that said processing apparatus can recover reliably said digital signals read from said medium, said recovery routine including microinstructions containing a limited number of constants representative of initial patterns and predicted results;

decoder means coupled to said control store for generating control signals in response to decoding microinstructions read out from said control store;

data recovery means operatively coupled to said decoder means and to said peripheral device for assembling into bytes said digital signals transferred by said device at a specified rate for transfer to said data processing system, said recovery means including;

a plurality of recovery error indicator storage circuits operative to monitor said transfer for generating signals indicative of the occurrence of error conditions during the assembling of said digital signals;

input means coupled to said control store addressing means, said input means being operative to receive an input signal for conditioning said addressing means to cause said control store to branch to said basic test routine microinstructions;

control transfer means coupled to said decoder means, to said store, to said device and to said data recovery to control signals from said decoder means during execution of microinstructions of said recovery routine to condition said data recovery means for receiving only groups of digital signals generated from said initial patterns and inhibiting transfers of said digital signals from said device; and

,

logic means coupled to said control store and to said plurality of indicator storage circuits, said logic means being conditioned by control signals from said decoding means to compare the states of said recovery indicator storage circuits with a pattern of signals received from said control store representative of the predicted states of said recovery indicator circuits as a result of applying said groups of digital signal patterns of a first block to said data recovery means for determining that said data recovery means is operating reliably.

3. The peripheral system of claim 2 wherein said microprogrammed processing apparatus includes an input circuit coupled to said data processing system for receiving a reset signal from said system, said input circuit being operative to produce said input signal in response to said reset signal for application to said input means.

4. The peripheral system of claim 2 wherein said format of each of said blocks includes preamble and postamble sets of digital synchronization signals bracketing each group of digital data signals, the number of said preamble synchronization signals generated from said initial patterns being selected to have a predetermined relationship to the number of preamble synchronization signals included in each block recorded to said medium.

5. The peripheral system of claim 4 wherein said predetermined relationship is to have the number of said digital synchronization signals of each of said preamble less than the number of preamble synchronization signals included in each block of data signals recorded on said medium and corresponding to a minimum number of signals required to synchronize the operation of said data recovery means to said specified rate said digital signals are received from said device.

6. The system of claim 5 wherein said microprogrammed processing apparatus includes a plurality of transfer paths for interconnecting said control store, said data recovery means and said logic means for transferring digital byte signals between said data processing system and said magnetic tape peripheral device and wherein

said basic test routines further include a plurality of initial test routines, said microprogrammed processing apparatus being conditioned by microinstructions read out from said control store during the execution of said initial routines to establish independently that said control store, each of said plurality of transfer paths and each of said means are operating properly prior to execution of said recovery routine.

7. The system of claim 5 where in said microprogrammed processing apparatus further includes:

a counter coupled to said control store to said decoder means and to said logic means, said counter being conditioned by said decoder means to receive initially an index counter read out from said control store;

clocking circuits for applying clock pulse signals to said counter for decrementing said counter to a predetermined count for generating timing strobe signals enabling the transfer of digital signals at said specified rate between said microprogrammed processing apparatus and said one device;

said data recovery means further including timing means coupled to said counter for generating signals for transferring said digital data signals through said data recovery means at said specified rate;

a first register coupled to said logic means and to said decoder means, said first register being conditioned by said decoder means to receive a preamble count read out from said control store indicative of a number of frames of preamble synchronization signals to be generated for each block of digital signals applied to said data recovery means;

a write buffer register coupled to said control transfer means and to said logic means; and

,

said control store after each occurrence of a strobe signal being operative to read out microinstructions for conditioning said decoder means to generate control signals for applying predetermined pattern of digital synchronization signals to said write buffer register for transfer through said data recovery means and for decrementing by one said count stored in said first register.

8. The peripheral system of claim 7 wherein said data recovery means further comprises:

a plurality of series coupled buffer registers, a first one of said buffer registers being coupled to said control transfer means and a last of said buffer registers for storing said assembled byte, each of said registers including a pair of bistable storage devices, each pair of a first one of the registers being individually associated with one of the plurality of channels; and

means for applying sets of clocking signal to each pair of said storage devices of said first register for storing pulses representative of said digital signals for subsequent transfer through said buffer registers; and

wherein

said recovery routine includes a data routine having a branch test microinstruction which when executed tests the count stored in said first register, said addressing means including branch control means operative in response to signals indicating that said count has been decremented to zero to cause said store to branch other microinstructions in said data routine, a first microinstruction for conditioning said decoder means to generate a signal indicating that said minimum number of preamble frames have been processed, another one of said microinstructions conditioning said decoder means to generate control signals for loading a predetermined bit pattern into said write buffer register for signaling the end of generating said preamble signals of the block and said branch control means being responsive to timing signals from said data recovery means to condition said decoder means to generate signals to set a predetermined one of said plurality of indicator storage circuits for signaling synchronization of each of said clocking means to said digital synchronization signals within said minimum number of frames corresponding to said preamble count indicative that all of said clocking means are operating without any degradation in performance.

9. The peripheral system of claim 8 wherein said predetermined patterns of digital signals applied to said write buffer register include pairs of signals corresponding to said input pattern and complement of said input pattern representative of phase encoded signals normally generated during time intervals defined by said sets of clocking signals, said predetermined bit pattern being coded as an all ONES pattern and said predetermined one of said indicator circuits when set signaling that said data recovery means is in a data mode for assembling said digital data signals of said first block.

10. The peripheral system of claim 8 wherein said microprogrammed processing apparatus further includes:

second and third registers coupled to said logic means, to said decoder means, and to said control store, said second and third registers respectively being conditioned by signals generated by said decoder means to store signals corresponding to an initial data pattern and a predicted results pattern read out from said control store, and wherein

said recovery routine further includes additional sequences of microinstructions which comprise said data routine and a sequence of microinstructions which comprise an analysis routine, said decoder means being conditioned by one of additional sequences of microinstructions of said data routine read out from said control store to generate a first set of control signals for applying repetitively signals representative of said data pattern to said write buffer register for generating patterns of said digital data signals of said first block and said decoder means being conditioned by microinstructions in said sequence of said analysis routine to generate a second set of control signals for comparing said states of said recovery indicator storage circuits and the contents of said third register and generating a signal verifying that said data recovery means is operating properly.

11. The peripheral system of claim 10 wherein said microprogrammed processing apparatus further includes a fourth register coupled to said logic means for storing an error pattern, said error pattern and said initial data pattern each is in a binary code having a number of bits corresponding to the number of channels, said binary code of said error pattern containing a predetermined number of binary ONES used for generating error patterns of digital data signals designating a predetermined number of channels which are expected to signal failure and wherein

said data recovery means further includes correction circuits coupled to said last buffer register and a preceding buffer register, said correction circuits being operative in response to error signals to correct the byte assembled in said last buffer register;

said decoder means in response to microinstructions generating signals for shifting by one said binary code of said error pattern to generate digital data signals containing error pattern for indicating failures in different channels and wherein said contents of said third register are coded to indicate the predicted error conditions resulting from the assembling of said digital data signals into bytes and indicate when said assembled bytes contain correctable and uncorrectable errors, said signal indicating that said data recovery means is operating properly by signaling said errors as being uncorrectable when said error patterns contain a predetermined number of binary ONES causing a corresponding number of said channels to signal failure.

12. The system according to claim 11 wherein said predetermined number has a value of one, said data pattern initially having a binary code containing one binary ONE and said error pattern initially having a binary code containing no binary ONES for generation of said digital data signals of said first block and said error pattern thereafter having a binary code having at least one binary ONE for generating error patterns of said digital data signals of succeeding blocks.

13. The system according to claim 11 wherein data recovery means further includes a plurality of channel failure storage circuits having inputs coupled to a first predetermined one of said buffer registers and operative to signal conditions indicative of a failure in different ones of said channels and the outputs of said channel failures storage circuits being coupled to a second predetermined one of said buffer registers for transferring signals to said register indicative of said channel failures, said last one of said registers being coupled to said logic means, and wherein said analysis routine includes a test sequence of microinstructions, said decoder means being responsive to said test sequence for generating signals for storing indications of said channel failure signals in said last register and comparing said error pattern contents of said fourth register with the contents of said last register for verifying that only the channels predicted to have failures signaled failure indicative of no interference between channels.

14. The peripheral system of claim 11 wherein said microprogrammed processing apparatus further includes:

a fifth register coupled to said logic means for storing a base pattern, said base pattern being in binary code having a number of bits corresponding to said number of channels, said base pattern initially having a binary code containing a binary ONE and wherein said recovery routine further includes microinstructions for specifying shift operations and logical operations, said decoder means being responsive to said microinstructions specifying said shift operations to generate signals for shifting by one bit position said binary codes of said base pattern, said data pattern and said error pattern and said decoder means being responsive to said microinstructions specifying logical operations to generate signals for logically combining said error pattern with said data pattern for generating said digital data signals for each of said blocks and for logically combining said base pattern and said shifted base pattern to produce a result error pattern which when combined with said data pattern produces digital data signals containing error patterns having a plurality of binary ONES for indicating failures in more than one channel.

15. The peripheral system of claim 11 wherein said data recovery means further includes a check circuit coupled to a last one of said buffer registers, said check circuit operative to perform a check upon an assembled byte in said last one of said registers and signal the occurrence of an uncorrectable error within said byte;

said check indicator storage circuits include a plurality of test indicator storage circuits, at least one of said storage circuits being coupled to said check circuit and others of said test indicator circuits being coupled to said logic means and predetermined ones of said recovery error indicator circuits for receiving signals indicative of testing each of said bytes assembled in said last register; and

,

said microprogrammed processing apparatus further including;

a sixth register operatively coupled to said decoder means, to said control store and to said test indicator circuits for storing signals indicative of the states of said test indicator circuits; and

,

memory means operatively coupled to said control store, to said decoder means and to said logic means, said memory means being conditioned by said decoder means to receive a predicted result pattern of digital signals from said control store indicative of the predicated states of said test indicator storage circuits;

said decoder means being conditioned by sequences of microinstructions of said data routine and analysis routine to generate control signals for conditioning said sixth register to store indications of said test indicator circuits during the testing of each byte and said decoder means being conditioned by microinstructions of said analysis routine at the end of transferring all of the bytes of said first block to generate signals for comparing the contents of said sixth register with said pattern from said memory means for verifying that said error recovery indicator circuits are operating properly during the assembling of each of said bytes of said first block.

16. The peripheral system of claim 14 wherein said analysis routine includes a recycle sequence of microinstructions, said decoder means being conditioned by branch test microinstructions in said analysis routine in the absence of a comparison between predicted and actual results of said recovery indicator circuits to generate signals for conditioning said branch control means to cause said control store to branch to said recycle sequence of microinstructions for repeating execution of said data routine to cause the generation of bytes of digital data signals containing error patterns identical to said bytes of the preceding generated block.

17. The peripheral system of claim 16 wherein said analysis routine further includes a return type microinstruction following said branch test microinstructions, said return microinstruction conditioning said decoder means in the absence of any branch produced by said branch test microinstructions indicative that all of the bytes of said block had been assembled correctly by said data recovery means to condition said branch control means to cause said control store to branch to repeat said data routine for generation of bytes of digital signals of a next block, said digital data signals being coded to contain error patterns of digital data signals different from those of said preceding block enabling testing of other channels of said data recovery means.

18. The peripheral system of claim 17 wherein said recovery routine includes a master sequence of microinstructions for specifying different indexes for enabling the transfer of digital signals from said device at different specified rates, said decoder means being conditioned successively by different ones of said microinstructions in said master sequence to generate signals for loading said counter with a different index to enable repeating the transfer of said digital signals of said block at said different specified rates for determining that said data recovery means is operating reliably at all of the corresponding device rates established by different device operating speeds.

19. the peripheral system of claim 18 wherein said master sequence further includes a final sequence of microinstructions, said decoder means in the absence of any error conditions resulting from said basic logic test routines being conditioned by said final sequence of microinstructions to generate signals to condition said branch control means for causing said control store to branch to a routine to perpare for receiving commands from said data processing system.

20. A peripheral controller coupled to a data processing system and to a plurality of magnetic tape devices operative to read and record frames of digital signals arranged in blocks on a multichannel magnetic medium, each block having a predetermined format, said controller including an addressable control store for storing microprograms used to perform said read and write operations, decoder circuits coupled to said control store for generating control signals in response to decoding microinstructions of said microprograms, a processing unit for performing arithmetic and logic operations upon a pair of operands, a data recovery unit and for assembling into bytes, digital signals transferred by said selected device at a specified rate for transfer to said date processing system, said recovery unit having an input coupled to receive digital signals from a selected device and an output coupled to said processing unit and including a plurality of recovery error indicator storage circuits operative to store signals indicative of error conditions occurring during the assembling of said digital signals received from said device, said controller further including self-testing apparatus comprising:

selector circuit means having an output and at least first and second inputs, said output being coupled to said input of said data recovery unit, said first inputs being coupled to said input of said selected device and said second input being coupled to said processing unit;

a first storage means operatively coupled to said data recovery error indicator storage circuits for storing signals indicative of error conditions detected by said recovery unit;

said control store including input means for receiving an input reset control signal from said data processing system and further including a plurality of basic test routines, one of said routines for verifying that said data recovery unit is operating properly, said one of said routines including a limited number of microinstructions containing constants corresponding to initial patterns and expected results patterns, said control store being responsive to said reset signal to branch to said basic test routines, said decoder circuits being conditioned by a first microinstruction sequence of said one routine to generate signals for conditioning said selector circuit means to connect said recovery unit to receive signals only from said second output and said decoder circuit being conditioned by repeated execution of other microinstructions of said one routine to generate signals for conditioning said processing means to generate digital signals of a first block from said initial patterns arranged in said predetermined format and said decoder means being conditioned by a sequence of test microinstructions upon completion of assembling into bytes said digital signals of said first block to generate signals to compare the states of said first storage means with one of said patterns of expected results for testing whether said recovery unit is operating reliably.

21. The controller according to claim 20 wherein each of said blocks includes preamble and postamble sets of digital synchronization signals bracketing each group of digital data signals, said processing unit being conditioned by said signals to generate a number of preamble synchronization signals selected to have a predetermined relationship to the number of preamble synchronization signals bracketing each block recorded on said medium.

22. The controller according to claim 21 wherein said predetermined relationship is to have the number of said digital synchronization signals of each preamble less than the number of preamble synchronization signals included in each block of data signals recorded on said medium and corresponding to a minimum number of signals required to synchronize the operation of said data recovery unit to the transfer rate of said digital signals received from said device.

23. The controller according to claim 21 wherein said controller further includes:

a counter coupled to said control store, said decoder circuits and to said processing unit, said counter being conditioned by said decoder circuits to receive initially an index count read out from said control store;

clocking circuits for applying clock pulse signals to said counter for decrementing said counter to a predetermined count for generating timing strobe signals enabling the transfer of digital signals at said specified rate between said processing unit and said device;

said data recovery means further including timing means coupled to said counter for generating signals for transferring said digital data signals through said data recovery unit at said specified rate;

a first register coupled to said processing unit, said first register being operative to receive from said processing unit a preamble count read out from said control store indicative of a number of frames of preambel synchronization signals to be generated for each block of digital signals applied to said data recovery unit;

a write buffer register coupled between said processing unit and said second unit; and

said control store conditioning said decoder circuits after each occurrence of a strobe signal to generate control signals for applying a predetermined pattern of digital synchronization signals to said write buffer register for transfer and assembling by said data recovery unit and for decrementing by said count stored in said first register.

24. The controller according to claim 20 wherein said controller includes a plurality of transfer paths for interconnecting said control store and first storage means, said processing unit and said recovery unit for transferring digital signals between said data processing system and a selected device and

wherein said basic test routines further include a plurality of initial test routines, said controller being conditioned by microinstructions read out from said control store during the execution of said initial test routines to establish independently that said control store, said means, each of said units and each of said transfer paths are operating properly prior to execution of said one routine.

25. The controller according to claim 23 wherein said data recovery unit further comprises:

a plurality of series coupled buffer registers, a first one of said buffer registers being coupled to said control transfer means and a last of said buffer registers for storing said assembled byte, each of said registers including a pair of bistable storage devices, each pair of a first one of the registers being individually associated with one of the plurality of channels; and

means for applying sets of clocking signal to each pair of said storage devices of said first register for storing pulses representative of said digital signals for subsequent transfer through said buffer registers; and

wherein

said one routine includes a data routine having a branch test microinstruction which when executed tests the count stored in said first register, said control store including branch control means operative in response to signals indicating that said count has been decremented to zero to cause said store to branch other microinstructions in said data routine, a first microinstruction for conditioning said decoder circuits to generate a signal indicating that said minimum number of preamble frames have been processed, another one of said microinstructions conditioning said decoder circuits to generate control signals for loading a predetermined bit pattern into said write buffer register for signaling the end of generating said preamble signals of the block and said branch control means being responsive to timing signals from said data recovery means to condition said decoder circuits to generate signals to set a predetermined one of said plurality of indicator storage circuits for signaling synchronization of each of said clocking means to said digital synchronization signals within said minimum number of frames corresponding to said preamble count indicative that all of said clocking means are operating without any degradation in performance.

26. The controller according to claim 25 wherein said controller further includes:

second and third registers coupled to said processing unit, said second and third registers respectively being conditioned by signals generated by said decoder means to store an initial data pattern and a predicated results pattern read out from said control store, and wherein

said one routine further includes additional sequences of microinstructions which comprise said data routine and a sequence of microinstructions which comprise an analysis routine, said decoder means being conditioned by one of additional sequences of microinstructions of said data routine read out from said control store to generate a first set of control signals for applying repetitively signals representative of said data pattern to said write buffer register for generating patterns of said digital data signals of said first block and said decoder means being conditioned by microinstructions in said sequence of said analysis routine to generate a second set of control signals for comparing said states of said first storage means and the contents of said third register and generating a signal verifying that said data recovery means is operating properly.

27. The controller of claim 26 wherein said controller further includes a fourth register coupled to said processing unit for storing an error pattern, said error pattern and said initial data pattern each is in a binary code having a number of bits corresponding to the number of channels, said binary code of said error pattern containing a predetermined number of binary ONES used for generating error patterns of digital data signals designating a predetermined number of channels which are expected to signal failure and wherein

said data recovery means further includes correction circuits coupled to said last buffer register and a preceding buffer register, said correction circuits being operative in response to error signals to correct the byte assembled in said last buffer register;

said decoder circuits in response to microinstructions generating signals for shifting by one said binary code of said error pattern to generate digital data signals containing error patterns for indicating failures in different channels and wherein said contents of said third register are coded to indicate the predicted error conditions resulting from the assembling of said digital data signals into bytes and indicate when said assembled bytes contain correctable and uncorrectable errors, said signal indicating that said data recovery means is operating properly by signaling said errors as being uncorrectable when said error patterns contain a predetermined number of binary ONES causing a corresponding number of said channels to signal failure.

28. The controller of claim 27 wherein said data recovery unit further includes a plurality of channel failure storage circuits having inputs coupled to a first predetermined one of said buffer registers and operative to signal conditions indicative of a failure in different ones of said channels and the outputs of said channel failure storage circuits being coupled to a second predetermined one of said buffer registers for transferring signals to said register indicative of said channel failures, said last one of said registers being coupled to said logic means, and wherein said analysis routine includes a test sequence of microinstructions, said decoder circuit being responsive to said test sequence for generating signals for storing indications of said channel failure signals in said last register and comparing said error pattern contents of said fourth register with the contents of said last register for verifying that only the channels predicted to have failures signaled failure indicative of no interference between channels.

29. The controller of claim 27 wherein said data recovery unit further includes a check circuit coupled to a last one of said buffer registers, said check circuit operative to perform a check upon an assembled byte in said last one of said registers and signal the occurrence of an uncorrectable error within said byte;

said check indicator storage circuits including a plurality of test indicator storage circuits, at least one of said storage circuits being coupled to said check circuit and others of said test indicator circuits being coupled to said processing unit and predetermined ones of said recovery error indicator circuits for receiving signals indicative of testing each of said bytes assembled in said last register; and

,

said controller further including;

a fifth register operatively coupled to said control store and to said test indicator circuits for storing signals indicative of the states of said test indicator circuits; and

,

memory means operatively coupled to said control store and to said logic means, said memory means being conditioned to receive a predicted result pattern of digital signals from said control store indicative of the predicted states of said test indicator storage circuits;

said decoder circuits being conditioned by sequences of microinstructions of said data routine and analysis routine to generate control signals for conditioning said fifth register to store indications of said test indicator circuits during the testing of each byte and said decoder circuits being conditioned by microinstructions of said anaylsis routine at the end of transferring all of the bytes of said first block to generate signals for comparing the contents of said fifth register with said pattern from said memory means for verifying that said error recovery indicator circuits are operating properly during the assembling of each of said bytes of said first block.

30. An improved method of initializing a magnetic tape peripheral subsystem in response to a control signal from a data processing system coupled to said peripheral system, said peripheral system including a microprogrammed input/output magnetic tape controller coupled to a plurality of magnetic tape devices for reading and recording on a multichannel medium successive bytes of digital signals in blocks, each block having a predetermined format, said controller including a control store for storing microprograms used for reading and recording said bytes and a data recovery unit coupled to receive signals from a selected one of said devices and assemble said signals into bytes for transfer to said data processing system, said recovery unit including a plurality of error indicator storage circuits for signaling the occurrence of error conditions during the assembling of said bytes, said improved method including the steps of:

storing in said control store a plurality of basic test routines, one of said test routines involving microinstructions containing constants representative of initial patterns used to generate groups of digital signal patterns which constitute blocks arranged in said predetermined format and patterns representative of expected results for verifying that said controller can recover reliably said signals from said medium;

generating signals by said controller in response to said control signal which conditions said control store to branch to said one of said test routines;

generating signals in response to microinstructions of said one of said test routines for connecting said data recovery unit to receive said generated groups of digital signals and inhibiting transfer of digital signals from a selected one of said plurality of magnetic tape devices;

generating said groups of digital signals from microinstructions containing constants representative of said initial patterns and applying them to said recovery unit;

monitoring the states of said error indicator storage circuits in said controller during the application of said groups of digital signals;

comparing a predetermined one of said patterns obtained from one of said microinstructions read from said control store indicating said expected results with the states of said error indicator storage circuits; and

signaling that said recovery unit is operating reliably in recovering said groups of digital signals when the states of certain ones of said indicator storage circuits indicate that said blocks applied to said recovery unit contain patterns of digital data signals representative of uncorrectable error conditions as defined by said predetermined one of said patterns.