Adaptive correction of phase errors in noncoherent demodulation of carrier asymmetrically modulated with digital signals

• US 4,048,572 A
• Filed: 12/20/1976
• Issued: 09/13/1977
• Est. Priority Date: 12/18/1975
• Status: Expired due to Term

• Current Assignee: Cselt - Centro Studi E Laboratori Telecommunicazioni SPA
• Original Assignee: Cselt - Centro Studi E Laboratori Telecommunicazioni SPA
• Inventors: Dogliotti, Renato, Mazzei, Umberto, Mengali, Umberto
• Primary Examiner(s): Kominski, John
• Application Number:
  US05/752,168
• Time in Patent Office: 267 Days
• Field of Search: 329/104, 329/107, 329/50, 329/110, 328/162, 328/163, 328/155, 325/480
• US Class Current: 375/371
• CPC Class Codes: H04L 27/066 Carrier recovery circuits H04L27/2271 takes precedence

Abstract

Digital signals asymmetrically modulated upon a carrier, with suppressed or vestigial second sideband, are recovered at a receiver by pseudo-coherent demodulation or periodic sampling and subsequent digitization to provide a train of raw data signals X from which a train of raw quadrature signals Y is derived by digital filtration. Signals X and Y are fed to a phase corrector where they are cross-multiplied with a sine function and a cosine function of a feedback signal W, approximating a corrective phase angle φ(t), to yield a corrected in-phase signal X'"'"' and a corrected quadrature signal Y'"'"'. Signal X'"'"' is quantized to provide a reference signal c which, upon subtraction from signal X'"'"', produces a bipolar difference signal whose sign bit is multiplied with either the entire signal Y'"'"' or its sign bit to provide an error signal V. The latter is averaged over a number of clock cycles, resulting in the feedback signal W whose trigonometric functions are read out from a memory for utilization in the generation of corrected signals X'"'"' and Y'"'"'.

Claims

1. A method of correcting distortions due to phase errors in a train of data signals recovered during successive clock cycles by noncoherent demodulation from an asymmetrically modulated carrier, comprising the steps of:

deriving a train of raw bipolar quadrature signals from the train of recovered raw bipolar data signals;

cross-multiplying said raw data signals and said raw quadrature signals with two mutually conjugate trigonometric functions of a magnitude substantially compensating said phase errors, thereby generating corrected bipolar in-phase signals and corrected bipolar quadrature signals;

generating a series of reference signals by quantizing said corrected in-phase signals;

obtaining a succession of bipolar difference signals by subtractively combining said corrected in-phase signals and said reference signals;

multiplying at least parts of said difference signals with at least parts of said corrected quadrature signals to produce bipolar error signals of a polarity which is the product of the polarities of said difference signals and of said corrected quadrature signals;

averaging said error signals over a plurality of clock cycles to obtain a succession of corrective bipolar feedback signals; and

deriving said trigonometric functions from said feedback signals.

2. A method as defined in claim 1 wherein all said bipolar signals are digitized and provided with sign bits representing their polarities, said error signals being produced by multiplying at least the sign bits of said corrected quadrature signals with the sign bits of said difference signals.

3. In a system for recovering a train of bipolar data signals during successive clock cycles by noncoherent demodulation from an asymmetrically modulated carrier, including a local time base for establishing said clock cycles and a component circuit for correcting distortion of said data signals due to phase errors, the improvement wherein said component comprises:

transformation means for deriving a train of raw bipolar quadrature signals from a train of recovered raw data signals;

an arithmetic unit with a first input for receiving said raw data signals, a second input connected to said transformation means for receiving said raw quadrature signals, a first output for emitting corrected bipolar in-phase signals, and a second output for emitting corrected bipolar quadrature signals;

decision means connected to said first output for producing a series of reference signals by quantizing said corrected in-phase signals;

algebraic summing means with input connections to said first output and to said decision means for generating a succession of bipolar difference signals by subtractively combining said corrected in-phase signals and said reference signals;

multiplication means connected to said algebraic summing means and to said second output for producing bipolar error signals of a polarity which is the product of the polarities of said difference signals and said corrected quadrature signals;

integrating means controlled by said time base and connected to said multiplication means for producing a succession of corrective bipolar feedback signals representative of phase angle;

conversion means connected to said integrating means for translating each of said feedback signals into a pair of conjugate trigonometric functions thereof; and

calculating means in said arithmetic unit inserted between said inputs and outputs thereof and connected to said conversion means for synthesizing said corrected in-phase and quadrature signals by cross-multiplying said raw data signals and said raw quadrature signals with said conjugate trigonometric functions.

4. The improvement defined in claim 3 wherein said raw data signals are digitized, said transformation means comprising a digital filter.

5. The improvement defined in claim 4 wherein said calculating means comprises a first digital multiplier with input leads connected to said first input and to said conversion means, a second digital multiplier with input leads connected to said second input and to said conversion means, a first digital adder inserted between output leads of said first multiplier and said first output, and a second digital adder inserted between output leads of said second multiplier and said second output.

6. The improvement defined in claim 5 wherein said conversion means comprises a memory storing said trigonometric functions, switch means controlled by said time base between said integrating means and an address input of said memory for reading out sine and cosine functions of a feedback signal during different portions of a clock cycle, and delay means inserted between each of said multipliers and a respective digital adder in said arithmetic unit for temporarily storing the products of one of said functions until the generation of the products of the other of said functions.

7. The improvement defined in claim 6, further comprising register means inserted between said integrating means and said switch means for storing during a clock cycle a multibit word constituting said feedback signal, said multibit word including a polarity-indicating sign bit and a plurality of modulus bits, and inversion means controlled by said switch means for complementing said modulus bits during one of said portions of a clock cycle.

8. The improvement defined in claim 4 wherein said multiplication means comprises logical circuitry for isolating a first polarity-indicating sign bit from each of said difference signals and a second polarity-indicating sign bit from each of said corrected quadrature signals and for assigning to each of said error signals a polarity-indicating sign bit indicative of the product of the polarities of said difference signals and corrected quadrature signals.

9. The improvement defined in claim 8 wherein said sign bits have a logical value 0 for positive polarities, said logical circuitry comprising an Exclusive-OR gate with inputs connected to receive said first and second sign bits.

10. The improvement defined in claim 9 wherein said multiplication means further comprises storage means with a sign-bit cell connected to said Exclusive-OR gate and with additional cells connected to said second output for receiving modulus bits of each of said corrected quadrature signals.

11. The improvement defined in claim 4 wherein said integrating means comprises a plurality of branch paths including respective digital multipliers for weighting said error signals with predetermined constants, a digital accumulator in each but one of said branch paths upstream of the respective digital multiplier thereof, and adding means with inputs connected to all said branch paths downstream of all said digital multipliers.

12. The improvement defined in claim 11 wherein said integrating means further comprises another digital accumulator downstream of said adding means.