Operational amplifier

• US 4,048,575 A
• Filed: 09/11/1974
• Issued: 09/13/1977
• Est. Priority Date: 09/11/1974
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Musa, Fuad H.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US05/505,196
• Time in Patent Office: 1,098 Days
• Field of Search: 330/22, 330/30 D, 330/35, 330/40, 307/304
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 2203/45508 the CSC comprising a voltage generating circuit as bias circuit for the CSC
• CPC Class Codes: H03F 2203/45648 the LC comprising two current sources, which are not cascode current sources
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45659 Controlling the loading circuit of the differential amplifier

Abstract

A family of operational amplifiers are described which utilize only MOSFET transistors as the active devices. These operational amplifiers exhibit an infinite input impedance and zero input offset and bias currents. The circuits are capable of operating over a wide range of DC supply voltages at extremely low DC current drain. An operational amplifier is shown which operates from a single positive DC supply voltage and which handles a wide range of input common mode voltage swings including some negative common mode voltages. Another operational amplifier is shown which operates from a combination of a single positive and a single negative supply voltage and which handles a wide range of positive and negative input common mode voltage swings.

Claims

1. An operational amplifier comprising:

A. a source of potential having at least a first and a second voltage level;

B. a first and a second differential amplifier, each of said differential amplifiers including;

C. differential input means for receiving two input signals to be compared, each of said differential input means comprising;

1. a first MOSFET input device having source, drain and gate electrodes;

2.

3. An operational amplifier as recited in claim 1 wherein said MOSFET devices of the first conductivity type are P-channel MOSFETs and wherein said MOSFET active load devices of a second conductivity type are N-channel MOSFETs.

7. An operational amplifier as recited in claim 3 wherein said MOSFET devices of a first conductivity type are P-channel MOSFETs and wherein said MOSFET active load devices of a second conductivity type are N-channel MOSFETs.

2. a second MOSFET input device having source, drain and gate electrodes;

3. said source electrodes of said first and said second input devices being connected together and being coupled to a MOSFET constant source means;

4. said gate electrode of said first input device being adapted to receive a first input signal to be compared;

said gate electrode of said second input device being adapted to receive a second input signal to be compared;

D. load means comprising active load devices coupled to said differential input means and coupled to one or more output terminals for producing an output signal responsive to said differential input means, said output terminal having a quiescent operating point and said load means comprises;

1. a first MOSFET load device having source, drain and gate electrodes;

2. a second MOSFET load device having source, drain and gate electrodes;

3. said source electrode of said first load device being connected to said source electrode of said second load device and to said first voltage level;

4. said drain electrode of said first load device being connected to said drain electrode of said first input device for forming a first output terminal;

5. said drain electrode of said second load device being connected to said drain electrode of said second input device for forming a second output terminal;

6. said gate electrode and said drain electrode of said first load device and said gate electrode and said drain electrode of said second load device each being coupled to a load bias means;

7. said second output terminal being coupled to said output means for providing an amplified output signal;

E. wherein said load bias means coupled to said output terminals and to said active load for generating a compensating response for stabilizing said quiescent operating point comprises;

1. a first resistor connected between said gate electrode of said first load device and said drain electrode of said same device;

2. a second resistor connected between said gate electrode of said second load device and said drain electrode of said same device; and

3. a conductor connecting said gate electrode of said first load device and said gate electrode of said second load device;

F. wherein said MOSFET devices of said differential input means of said first differential amplifier are of a first conductivity type;

G. said MOSFET active load devices of said load means of said first differential amplifer are of a second conductivity type opposite to said first conductivity type;

H. said MOSFET devices of said differential input means of said second differential amplifier are of said second conductivity type; and

I. said MOSFET active load devices of said load means of said second differential amplifier are of said first conductivity type; and

said operational amplifier further includes;

J. a MOSFET biasing network connected between said first and said second voltage level for providing a first reference voltage and a second reference voltage;

K. a first MOSFET constant current source means coupled to said differential input means of said first differential amplifier, responsive to said first reference voltage for providing a first constant current; and

L. a second MOSFET constant current source means coupled to said differential input means of said second differential amplifier, responsive to said second reference voltage for providing a second constant current.

4. An operational amplifier comprising:

A. a source of potential having at least a first and a second voltage level;

B. a first and a second differential amplifier, each of said differential amplifiers including;

C. differential input means for receiving two input signals to be compared, each of said differential input means comprising;

1. a first MOSFET input device having source, drain and gate electrodes;

2. a second MOSFET input device having source, drain and gate electrodes;

3. said source electrodes of said first and said second input devices being connected together and being coupled to a MOSFET constant current source means;

4.

5. said gate electrode of said first input device being adapted to receive a first input signal to be compared;

said gate electrode of said second input device being adapted to receive a second input signal to be compared;

D. load means comprising active load devices coupled to said differential input means and coupled to one or more terminals for producing an output signal responsive to said differential input means, said output terminal having a quiescent operating point and said load means comprises;

1. a first MOSFET load device having source, drain and gate electrodes;

2. a second MOSFET load device having source, drain and gate electrodes;

3. said source electrode of said first load device being connected to said source electrode of said second load device and to said first voltage level;

4. said drain electrode of said first load device being connected to said drain electrode of said first input device for forming a first output terminal;

5. said drain electrode of said second load device being connected to said drain electrode of said second input device for forming a second output terminal;

6. said gate electrode and said drain electrode of said first load device and said gate electrode and said drain electrode of said second load device each being coupled to a load bias means;

7. said second output terminal being coupled to said output means for providing an amplified output signal;

E. wherein said load bias means coupled to said output terminals and to said active load for generating a compensating response for stabilizing said quiescent operating point comprises;

6. a conductor interconnecting said drain electrode of said first load device, said gate electrode of said same device and said gate electrode of said second load device;

2. a resistor connected between said gate electrode of said second load device and said drain electrode of said same device; and

3. a conductor connecting said gate electrode of said first load device and said gate electrode of said second load device;

F. wherein said MOSFET devices of said differential input means of said first differential amplifier are of a first conductivity type;

G. said MOSFET active load devices of said load means of said first differential amplifier are of a second conductivity type opposite to said first conductivity type;

H. said MOSFET devices of said differential input means of said second differential amplifier are of said second conductivity type; and

I. said MOSFET active load devices of said load means of said second differential amplifier are of said first conductivity type; and

said operational amplifier further includes;

J. a MOSFET biasing network connected between said first and said second voltage level for providing a first reference voltage and a second reference voltage;

K. a first MOSFET constant current source means coupled to said differential input means of said first differential amplifier, responsive to said first reference voltage for providing a first constant current, and

L. a second MOSFET constant current source means coupled to said differential input means of said second differential amplifier, responsive to said second reference voltage for providing a second constant current.