Complex pulse repetition frequency generator
First Claim
1. A complex pulse repetition frequency generator for generating a pulse repetition frequency signal having programmable stagger intervals comprising:
- a. clock means for generating a plurality of standard clock frequency signals;
b. memory address control means for generating a plurality of memory address signal sequences, each said memory address signal sequence having a start address and a stop address;
c. data memory means for producing a series of stagger data pulses in response to each said memory address signal sequence; and
,d. digitally programmable delay generating means for producing a pulse repetition frequency signal having stagger intervals generated in response to said series of stagger data pulses and to said clock frequency signals.
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Abstract
A complex pulse repetition frequency generator for producing a pulse repeion frequency (PRF) signal having programmable stagger intervals. The device consists of a clock for selecting one of a series of standard clock pulses which are used to increment a counter. A comparator compares the accumlated clock pulses with a stagger data output signal produced by a data memory source. When the outputs are equal, the comparator produces a PRF output pulse. Two data memory bands are provided; a random access memory in which stagger data can be programmed by a series of switches, and a preprogrammed read-only memory. Address counters are used with each memory unit and provide capability for addressing selected memory locations from the data memory sources. A pulse width generator allows the operator to vary the pulse width and utilizes an injection lock oscillator to prevent jitter whenever a standard clock pulse is used which is not an even multiple of a hundred nanoseconds.
44 Citations
13 Claims
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1. A complex pulse repetition frequency generator for generating a pulse repetition frequency signal having programmable stagger intervals comprising:
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a. clock means for generating a plurality of standard clock frequency signals; b. memory address control means for generating a plurality of memory address signal sequences, each said memory address signal sequence having a start address and a stop address; c. data memory means for producing a series of stagger data pulses in response to each said memory address signal sequence; and
,d. digitally programmable delay generating means for producing a pulse repetition frequency signal having stagger intervals generated in response to said series of stagger data pulses and to said clock frequency signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification