Fault-tolerant cell addressable array
First Claim
1. A defect-tolerant cell addressable array comprising:
- a. an array of functional cells arranged in rows and columns;
b. cell selection means responsive to cell address code signals for selectively addressing an individual functional cell in a respective row and column;
c. a plurality of redundant functional cells;
d. memory means in which cell address codes of defective functional cells indicative of row and column locations are selectively storable, said memory means being responsive to said cell address code signals for detecting when the cell address code signals correspond to the address codes of defective ones of said functional cells and for generating a signal indicative thereof; and
e. logic means responsive to the signal generated by said memory means for selecting a corresponding one of said redundant functional cells and for inhibiting the selection of the respective defective cell of said array.
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Accused Products
Abstract
A small programmable memory means such as an electrically programmable logic array is incorporated on the chip of a conventional bit addressable random access memory or other cell addressable array circuit. The array has one or more superfluous rows and/or columns of cells held in reserve. Processing and testing of the chip is conducted in a conventional manner. Chips with faulty cells are corrected by programming the memory means with the cell addresses of the faulty cell locations. Subsequently, the memory means will respond to any of these addresses and, through interaction with either the address decoding logic or input/output logic, cause a reserve cell or the contents thereof to be selected instead of the faulty cell.
241 Citations
54 Claims
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1. A defect-tolerant cell addressable array comprising:
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a. an array of functional cells arranged in rows and columns; b. cell selection means responsive to cell address code signals for selectively addressing an individual functional cell in a respective row and column; c. a plurality of redundant functional cells; d. memory means in which cell address codes of defective functional cells indicative of row and column locations are selectively storable, said memory means being responsive to said cell address code signals for detecting when the cell address code signals correspond to the address codes of defective ones of said functional cells and for generating a signal indicative thereof; and e. logic means responsive to the signal generated by said memory means for selecting a corresponding one of said redundant functional cells and for inhibiting the selection of the respective defective cell of said array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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9. The defect-tolerant cell addressable array according to claim 67 wherein said field programmable logic array or read-only memory array is comprised of semiconductor avalanche induced migration devices.
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21. A defect-tolerant cell addressable array comprising:
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a. an array of functional cells arranged in rows and columns; b. cell selection means responsive to row and column address code signals for selectively addressing an individual functional cell in a respective row and column; c. at least one redundant row or column of functional cells; d. programmable or programmed memory means coupled to receive said row and column address code signals for detecting the address codes of defective ones of said functional cells and generating a signal indicative thereof, said memory means including means for storing the row and column address codes of one or more defective cells of said array of functional cells; and e. logic means coupled to said memory means and responsive to the generated signal for selecting a corresponding functional cell in said redundant row or column each time a defective cell is detected by said memory means and for inhibiting the selection of the addressed defective cell. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49)
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50. A system of defect-tolerant cell addressable arrays comprising:
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a. a plurality of arrays of functional cells each being arranged in rows and columns; b. at least one redundant row or column of functional cells associated with each of said arrays; c. cell selection means responsive to row, column and array address code signals for selectively addressing an individual cell in a respective row, column and array; d. programmable or programmed memory means coupled to receive said row, column and array address code signals for detecting the address codes of defective ones of said functional cells and generating a signal indicative thereof, said memory means including means for storing the row, column and array address codes of one or more defective cells of said arrays of functional cells; and e. logic means coupled to said memory means and responsive to the generated signal for selecting a corresponding functional cell in the redundant row or column of said addressed array each time a defective cell is detected by said memory means and for inhibiting the selection of the addressed defective cell. - View Dependent Claims (51, 52, 53, 54)
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Specification