Apparatus and method for increasing the efficiency of random access storage

• US 4,051,355 A
• Filed: 04/29/1976
• Issued: 09/27/1977
• Est. Priority Date: 04/29/1976
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: NCR Corporation
• Inventors: Lin, Juei-po
• Primary Examiner(s): Dildine, Jr., R. Stephen
• Application Number:
  US05/681,675
• Time in Patent Office: 516 Days
• Field of Search: 235/153 AM, 340/173 BB, 340/174 ED
• US Class Current: 714/15
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1076 Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• CPC Class Codes: G06F 11/141 for bus or memory accesses
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

Apparatus and method are described wherein the average access time utilized for recovering stored data in a random access storage system is reduced. An access cycle is begun with the predetermined typical data bit delivery time known and with the knowledge of the worst case data bit delivery time. An output buffer is connected to a random access storage for receiving the data bits of an output message from the storage. The output buffer is gated to receive the data from the random access storage; the gate signal enables the output buffer to receive data bits over a predetermined time interval. The output buffer is connected to a data transmission means such as a bus, and is gated by a second signal to place the stored information on the bus. The second signal, the message gate signal, is timed to place the information stored in the output buffer on the bus during the period beginning with the typical data bit delivery time and ending after the worst case data bit delivery time. Thus, the data bits may be received from the random access storage and subsequently or immediately transmitted by the output buffer depending on the time of arrival of the data bit at the output buffer. Parity checking means check the parity of the message being transmitted from the random access storage to the output buffer; at the end of the time allowed for the worst case data bit delivery time the condition of the parity check means is ascertained, and if an incorrect parity condition exists an error/retry signal is generated to begin a retry cycle to again transmit the contents of the output buffer to the bus.

Claims

1. An improved method for receiving a message, having data bits therein, from a random access storage and transmitting said message, said data bits having a typical data bit delivery time and a worst case data bit delivery time, comprising the steps of:

a. storing said data bits in a buffer as they are received from a random access storage;

b. simultaneously transmitting said data bits from said buffer for a predetermined period of time ending after said worst case data bit delivery time;

c. checking the parity of said message as the data bits therein are stored in said buffer;

d. generating an error signal, when message is being transmitted to the bus and non-parity occurs.

2. The method of claim 1 including the additional step of:

retransmitting said data bits from said buffer after said error signal has been generated.

3. An improved method for receiving a message having data bits therein from a random access storage and transmitting said message, said data bits having a typical data bit delivery time and a worst case data bit delivery time, comprising the steps of:

a. storing said data bits in a buffer as they are received from a random access storage;

b. simultaneously transmitting said data bits from said buffer for a predetermined period of time beginning at said typical data bit delivery time and ending after said worst case data bit delivery time;

c. checking the parity of said message as the data bits therein are stored in said buffer;

d. generating an error signal, when message is being transmitted to the bus and non-parity occurs.

4. Method set forth in claim 3 including the additional step of retransmitting said data bits after said error signal has been generated.

5. In a random access storage system including a random access storage device for storing data messages comprising a plurality of data bits said system having a typical data bit delivery time and a worst case data bit delivery time, apparatus for decreasing the average access time of said system comprising:

a. a data bus for transmitting data;

b. an output buffer connected to said random access storage device responsive to an output buffer clock signal level for receiving and temporarily storing data bits from said device, and connected to said data bus and responsive to a data gate signal level for transmitting temporarily stored data to said bus;

c. parity check means connected to said random access storage device for checking parity of messages delivered to said output buffer from said random access storage device and for generating a non-parity signal when message parity is incorrect;

d. timing means connected to said output buffer for generating an output buffer clock signal level beginning before said typical data bit delivery time to enable said output buffer to receive and temporarily store said data bits and for generating a data gate signal level beginning at said typical data bit delivery time and ending after said worst case data bit delivery time to enable said output buffer to transmit temporarily stored data to said data bus.

6. The apparatus set forth in claim 5 wherein said output buffer clock signal ends at the same time as said data gate signal level.

7. The apparatus set forth in claim 5 including means responsive to the existence of said non-parity signal when message is being transmitted for generating an error/retry signal.

8. The apparatus set forth in claim 7 wherein said output buffer clock signal ends at the same time as said data gate signal level.

9. The apparatus set forth in claim 7 including means responsive to said error/retry signal for generating a second data gate signal level to retransmit the data bits stored in said output buffer.