Multiplexer receiver terminator

• US 4,052,567 A
• Filed: 12/24/1975
• Issued: 10/04/1977
• Est. Priority Date: 12/24/1975
• Status: Expired due to Term

• Current Assignee: DDI Communications Incorporated
• Original Assignee: DDI Communications Incorporated
• Inventors: MacKay, William Allan
• Primary Examiner(s): Stewart, David L.
• Application Number:
  US05/644,102
• Time in Patent Office: 650 Days
• Field of Search: 179/15 AL, 179/15 BA, 179/15 A, 179/15 R, 179/18 FC, 307/234
• US Class Current: 370/458
• CPC Class Codes: G08C 15/06 successively, i.e. using time division
• CPC Class Codes: H04J 3/1641 Hierarchical systems

Abstract

A multiplexer receiver terminator is disclosed for connection to a multiplexer receiver in a system having a plurality of multiplexer receivers connected on a common communication line. Each of the multiplexer receivers is assigned a time period for reception relative to a multiplexer time clock. The improvement includes a counter circuit connected to the multiplexer time clock for providing a counter output upon the clock counter counting between two preselected clock counts which correspond to the time period assigned for reception of the multiplexer receiver. A line receiver is connected to the communication line for providing an output upon detecting a predetermined period of signal absence on the communication line. The line receiver output is connected to the counter for resetting the counter after the predetermined period of signal absence. The counter circuit is connected to the multiplexer receiver for enabling reception from the communication line only during an output of the counter circuit. The foregoing abstract is merely a resume of one general application, is not a complete discussion of all principles of operation or applications, and is not to be construed as a limitation on the scope of the claimed subject matter.

Claims

1. A device for a multiplexer receiver in a system having a plurality of multiplexer receivers connected on a common communication line wherein each multiplexer receiver has a time period for reception relative to a multiplexer time clock, comprising in combination:

a counter circuit connected to the multiplexer time clock for providing a counter output upon registering a clock count between two preselected clock counts which correspond to the time period of the multiplexer receiver;

a line receiver connected to the communication line for providing a line receiver output upon detecting a predetermined period of signal absence on the communication line;

means connecting said line receiver output to said counter circuit for resetting said counter circuit after said predetermined period of signal absence;

and means connecting said counter circuit output to the multiplexer receiver for enabling reception from the communication line only during a counter output of said counter circuit.

2. A device as set forth in claim 1, wherein said means connecting said counter circuit to the multiplexer receiver includes means for enabling the multiplexer receiver a predetermined time after said counter output.

3. A device as set forth in claim 1, wherein said line receiver includes a pause counter having a reset input;

means connecting said pause counter to the multiplexer time clock for providing said line receiver output upon counting a given number of clock counts;

and means connecting said reset input to the communication line for resetting said pause counter when a signal occurs on the communication line.

4. A device as set forth in claim 1, including means for deactivating the device for a given duration immediately after operating power is applied.

5. A device as set forth in claim 1, wherein said means connecting said counter circuit to the multiplexer receiver includes a counter monostable providing a first and a second output sequentially in time upon a counter output;

a pause counter connected to the multiplexer time clock for providing a pause counter output upon counting a given number of clock counts;

a gate connected between said pause counter and the multiplexer receiver;

means connecting said first output of said counter monostable to initiate counting by said pause counter;

and means connecting said second output of said counter monostable for enabling said gate to transfer said pause counter output to the multiplexer receiver.

6. A device as set forth in claim 1 including means for varying said preselected clock counts to correspond to a specific time period assigned to the multiplexer receiver.

7. A device as set forth in claim 6, wherein said means for varying said preselected clock count includes said clock counter having a plurality of outputs with the combination thereof providing a numerical output of the count of the counter;

and means for connecting selected ones of said plurality of clock counter outputs to provide said counter output when a common signal exists on said selected outputs.

8. A device as set forth in claim 1, including means for visually indicating the transfer of information on the communication line by the multiplexer.

9. A device for a multiplexer receiver which receives plural information in a system having a plurality of multiplexer receivers on a common communication line wherein each multiplexer receiver is assigned a time period for reception relative to a multiplexer time clock, comprising in combination:

a clock counter connected to the multiplexer time clock for providing a counter output upon registering a clock count between a first and a second preselected clock counts which correspond to the time period assigned to the multiplexer receiver;

means for varying said preselected clock counts of said counter circuit to correspond to the time period assigned to the multiplexer receiver;

a line receiver connected to the communication line for providing a line receiver output upon detecting a predetermined period of signal absence on said communication line;

means connecting said line receiver output to said counter circuit for resetting said counter circuit after said predetermined period of signal absence;

means connecting said counter circuit to the multiplexer receiver for enabling reception of the plural information from the communication line upon said clock counter counting said first preselected clock count;

and means for disenabling reception of the plural information from the communication line upon said clock counter counting said second preselected clock count.

10. A device as set forth in claim 9, wherein said counter provides a first clock counter output upon counting said first preselected clock count;

means connecting said first clock counter output for resetting said clock counter;

and said counter providing a second clock counter output upon counting said second preselected clock count.

11. A device as set forth in claim 10, wherein said means connecting said counter circuit to the multiplexer receiver includes a first and a second clock latch circuit;

said first clock latch circuit enabling reception by the multiplexer receiver upon receiving said first clock counter output of said clock counter;

said second clock latch circuit disenabling reception by the multiplexer receiver upon receiving said second clock counter output of said clock counter;

and means interconnecting said first and second clock latch circuit for providing alternating operation between said first and second clock latch circuits.

12. A device as set forth in claim 9, wherein said means connecting said counter circuit to the multiplexer receiver includes gate means.

13. A device for connection to one of a plurality of multiplexer receivers on a communication line wherein each multiplexer receiver is assigned a unique reception period relative to a multiplexer clock generating clock pulses, comprising in combination:

a programmable clock counter connected to the multiplexer clock for providing a first and a second clock counter output upon counting a first and a second preprogrammed number of multiplexer clock pulses which correspond to the beginning and the end of the unique reception period, respectively;

means connecting said clock counter for initiating reception of the multiplexer receiver on the communication line upon said programmable counter counting said first preprogrammed number of clock pulses;

means connecting said clock counter for terminating reception of the multiplexer receiver on the communication line upon said programmable counter counting said second preprogramed number of clock pulses;

and means initiating said clock counter to count said preprogramed number of clock pulses upon silence existing on the communication line for a predetermined period.

14. A device for a multiplexer receiver which receives plural information on a communication line having a plurality of multiplexer receivers connected thereto wherein each multiplexer receiver is assigned a specific time period for reception relative to a multiplexer time clock generating clock pulses, comprising in combination:

a programmable clock counter connected to the multiplexer time clock for providing a first clock counter output upon counting a first preprogramed number of clock pulses which corresponds to the beginning of the specific time period assigned to the multiplexer receiver;

said clock counter providing a second clock counter output upon counting a second preprogramed number of clock pulses which corresponds to the end of the specific time period assigned to the multiplexer receiver;

a pause counter connected to the multiplexer time clock for providing a first and a second pause output upon counting a first and a second preselected number of clock pulses, respectively;

means connecting said first output of said clock counter to said pause counter to commence counting of said first preselected number of clock pulses;

means connecting said first pause counter output for enabling the multiplexer receiver to initiate reception of the plural information on the communication line;

means connecting said second output of said clock counter for disenabling the receiver to terminate reception of the plural information on the communication line;

means connecting said pause counter to the communication line for providing said second pause output upon a silence existing on the communication line exceeding said second preselected number of multiplexer clock pulses;

and means connecting said pause counter to said clock counter for initiating counting of said clock counter upon said second pause output.