Circuit for interfacing microcomputer to peripheral devices

• US 4,052,702 A
• Filed: 05/10/1976
• Issued: 10/04/1977
• Est. Priority Date: 05/10/1976
• Status: Expired due to Term

• Current Assignee: Kenway Corporation
• Original Assignee: Kenway Corporation
• Inventors: Black, Francis B., Smith, Kay D., Bachass, Arjun S.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Heckler, Thomas M.
• Application Number:
  US05/684,616
• Time in Patent Office: 512 Days
• Field of Search: 340/172.5, 235/150, 178/50, 179/15 BA, 179/15 BV
• US Class Current: 710/60
• CPC Class Codes: B65G 1/0421 with control for stacker crane operations
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06Q 10/08 Logistics, e.g. warehousing, loading or distribution; Inventory or stock management

Abstract

A microcomputer for controlling an automated materials handling system, the microcomputer having a novel interface circuit permitting direct interface with a wide variety of peripheral devices, both serial and parallel and at any one of a variety of communication rates selected to maximize machine efficiency under a wide range of noise conditions. A safety relative timer circuit terminates operation of the machine if the S/R machine does not complete a task within a predetermined time increment.

Claims

1. An interface circuit for interfacing a plurality of serial channel peripheral devices to a CPU of a microcomputer, the interface circuit having a plurality of serial channels and further comprising:

means for simultaneously generating a plurality of baud rates;

a plurality of means electrically connected to the generating means for selecting a predetermined one of the baud rates, each of said selecting means having means for communicating a predetermined one of the baud rates to one of the serial channels;

means electrically connected to each selecting means for gating data serially over one of the serial channels at the selected baud rate to one of the serial channel peripheral devices; and

means for communicating data from the CPU to each gating means.

2. An interface circuit as defined in claim 1 wherein said generating means comprises a frequency generating crystal and at least one frequency divider for outputting a plurality of frequencies.

3. An interface circuit as defined in claim 2 wherein said plurality of frequencies comprise at least multiples of the following frequencies expressed in Hz:

110, 150, 300, 1200, 1800, 2400, 4800 and 9600.

4. An interface circuit as defined in claim 1 wherein each said selecting means comprises a baud rate selection register into which baud rate selection data is loaded from the CPU, each said selecting means further comprising a multiplexer for receiving the plurality of baud rates from the generating means and also receiving output from the baud rate selection register, the multiplexer transmitting one of the plurality of baud rates to one of the gating means in response to the output from the baud rate selection register.

5. An interface circuit as defined in claim 1 wherein each said gating means comprises an asynchronous communication interface adaptor into which output data and control data is selectively loaded from the CPU, the interface circuit further comprising means for communicating output and control data to each adaptor, each said adaptor comprising means for enabling the adaptor to send the output data over the serial channel at the selected baud rate to the peripheral device in response to the control data.

6. An interface circuit for interfacing a microcomputer having a CPU to at least two distinct peripheral devices, each peripheral device communicating serially with the interface circuit over one of a plurality of output channels provided in the interface circuit, the interface circuit further comprising in combination:

a baud rate selection register and means for communicating baud rate selection data from the CPU to the baud rate selection register;

a baud rate generator for generating a plurality of baud rates;

a clock generator;

transmitting means electrically connected to the baud rate generator, baud rate selection register and clock generator, said transmitting means responding to the data in the baud rate selection register so as to transmit a selected one of the plurality of generated baud rates to the clock generator, thereby driving the clock generator at the selected baud rate;

means for enabling one of the output channels, the enabling means comprising a channel select circuit and means for communicating address data from the CPU to the channel select circuit so as to permit the channel select circuit to enable a predetermined one of the output channels in response to a preselected combination of address signals from the CPU;

means for converting parallel format data from the CPU to serial format data, said converting means also being electrically connected to the clock generator and comprising means responsive to the clock generator for gating the serial format data over the selected output channel at the selected baud rate to a peripheral device; and

means for communicating the parallel format data from the CPU to the converting means.

7. An interface circuit as defined in claim 6 wherein said transmitting means comprises a multiplexer circuit which receives the output of the baud rate generator;

means for communicating the baud rate selection data from the baud rate selection register to the multiplexer; and

means for isolating the selected baud rate so that only the selected baud rate is communicated to the clock generator.

8. An interface circuit as defined in claim 6 wherein said means for gating the serial format data over the selected output channel comprises a photo coupler for optically isolating the transmitted data.

9. An interface circuit for a microcomputer having a CPU which communicates only in parallel, said interface circuit interfacing the CPU to at least two peripheral devices, one of the peripheral devices communicating serially with the interface circuit and the other peripheral device communicating in parallel with the interface circuit, the interface circuit having at least one serial channel for accommodating serial communication in both the transmit and receive modes and at least one parallel channel for accommodating parallel communication in both the transmit and receive modes, said interface circuit further comprising:

a serial channel integrated circuit adaptor connected to the serial channel, said adaptor comprising means for receiving address and read-write control signals from the CPU and means for communicating data between the CPU and serial channel peripheral device, said communicating means comprising means for two-way conversion of data format between parallel format and serial format;

a parallel channel integrated circuit adaptor connected to the parallel channel, said adaptor comprising means for receiving address and read-write control signals from the CPU and means for communicating parallel format data between the CPU and parallel communicating peripheral device;

means for selecting one of the channels for communicating data between the CPU and one of the peripheral devices, said selecting means comprising means for transmitting address signals from the CPU to the address signal receiving means of each adaptor, the address signals comprising a unique code effective to enable a predetermined one of the channels to communicate data between the CPU and one of the peripheral devices, said selecting means further comprising means for transmitting the read-write control signal from the CPU to the read-write signal receiving means of each adaptor, the read-write signal determining one of the transmit and receive modes for the selected channel;

a baud rate generator for generating a plurality of baud rates; and

means electrically connected to the baud rate generator for selecting a predetermined one of the baud rates, said baud rate selecting means being also connected to the two-way data format conversion means so as to accommodate serial communication between the CPU and the serial channel peripheral device at the selected baud rate when the serial channel has been selected for communication.

10. An interface circuit for interfacing a microcomputer having a CPU to a plurality of serial-channel peripheral devices and a purality of parallel-channel peripheral devices, the interface circuit having a plurality of serial channels and a plurality of parallel channels and further comprising:

means for generating a plurality of baud rates;

an interface adaptor for each serial channel, the interface adaptor comprising means for receiving both output data and control data from the CPU in parallel format, said adaptor further comprising means for converting parallel format data to serial format data, and a clock generator electrically connected to said converting means, the clock generator gating serial format data through the converting means onto a selected serial channel at a preselected baud rate;

a baud rate selection register;

means for transmitting baud rate selection data from the CPU to the baud rate selection register;

multiplexing means electrically connected to the baud rate generating means, baud rate selection register, and the clock generator, said multiplexing means responding to the data in the baud rate selection register so as to transmit a selected one of the plurality of generated baud rates to the clock generator, thereby driving the clock generator at the selected baud rate;

a parallel channel adaptor comprising means for receiving both output data and control data from the CPU in parallel format, said adaptor further comprising gating means electrically connected to said receiving means for gating parallel format data onto a selected parallel channel;

means for communicating output data from the CPU to each adaptor; and

means for communicating control data from the CPU to each adaptor, said control data comprising a preselected combination of address signals which will enable the data receiving means of only one adaptor at a time to receive output data from the CPU.

11. An interface circuit for interfacing a CPU as defined in claim 10 further comprising means for receiving input data from said peripheral devices, means for determining the direction of data travel between the CPU and the peripheral devices, said determining means comprising interrupt logic for selectively accessing the CPU when the interface circuit is ready to transmit or receive data, and means connected to said determining means for communicating a read-write control signal from the CPU to the determining means.

12. An interface circuit as defined in claim 10 wherein one of the said plurality of parallel-channel peripheral devices is a CPU of a second, remote microcomputer.

13. A method of interfacing a CPU through an interface circuit having a plurality of serial channels to a plurality of serially communicating peripheral devices, each peripheral device being designed to operate at a predetermined baud rate, the method comprising the steps of:

simultaneously generating a plurality of baud rates in the interface circuit;

selecting a baud rate for each serial channel that is compatible with the design of the peripheral device communicating over that channel;

communicating data from the CPU to each serial channel in the interface circuit;

enabling one of the serial channels; and

serially gating the data at the selected baud rate over the enabled serial channel to one of the peripheral devices.

14. A method as defined in claim 13 wherein said selecting step comprises transmitting baud rate selection data from the CPU to the interface circuit, the interface circuit thereafter responding to the data so as to select a baud rate for each serial channel that is compatible with the design of the peripheral device that communicates over that channel.

15. A method of interfacing a CPU of a microcomputer through an interface circuit having a plurality of both serial and parallel bi-directional data channels to a plurality of both parallel and serial channel peripheral devices, the method comprising the steps of:

sending address and read-write instruction signals to both the serial and parallel data channels;

selecting one of the data channels for communicating data between the CPU and one of the peripheral devices, said selecting step comprising enabling only one of the serial or parallel data channels in response to the address instruction signals;

determining the directional flow of data between the CPU and one of the peripheral devices in response to the read-write instruction signals;

simultaneously generating a plurality of baud rates;

selecting a baud rate for each serial channel that is compatible with the design of the peripheral device communicating over that channel; and

communicating the data through the enabled data channel in the selected direction, said data communicating step comprising communicating data at the selected baud rate whenever a serial channel is enabled.

16. A method of interfacing a CPU through an interface circuit having a plurality of both serial and parallel data channels, each channel comprising an interface adaptor, the interface circuit further having a baud rate generator, a plurality of multiplexers connected to the output of the baud rate generator, and a timing clock internal to each serial channel adaptor and connected to the output of one of the multiplexers, the CPU being interfaced to a plurality of serial and parallel channel peripheral devices, and the method comprising the steps of:

communicating address data from the CPU to each of the interface adaptors, and enabling a preselected one of the adaptors in response to the address data;

generating a plurality of baud rates and communicating the plurality of baud rates to the multiplexers;

transmitting baud rate selection instructions from the CPU to the multiplexers and thereafter transmitting from one of the multiplexers a selected one of the plurality of baud rates to the timing clock internal of a corresponding adaptor so as to drive the clock at the selected baud rate; and

communicating data between the peripheral device and the microcomputer through the selected interface adaptor, said data being communicated at the selected baud rate by the timing clock when a serial channel adaptor is enabled.

17. A method as defined in claim 16 further comprising generating a read-write signal and instructing the enabled adaptor as to the direction of data transfer in accordance with the state of the read-write signal.

18. An interface circuit for interfacing a plurality of serial channel peripheral devices to a CPU of a microcomputer, the interface circuit having a plurality of serial channels and further comprising:

means for simultaneously generating a plurality of baud rates;

a plurality of means electrically connected to the generating means for selecting a predetermined one of the baud rates, each of said selecting means having means for communicating a predetermined one of the baud rates to one of the serial channels;

means electrically connected to each selecting means for serially receiving data from one of the peripheral devices at the selected baud rate over one of the serial channels; and

means for communicating the data from the interface circuit to the CPU.

19. A method of interfacing a CPU through an interface circuit having a plurality of serial channels to a plurality of serially communicating peripheral devices, each peripheral device being designed to operate at a predetermined baud rate, the method comprising the steps of:

simultaneously generating a plurality of baud rates in the interface circuit;

selecting a baud rate for each serial channel that is compatible with the design of the peripheral device communicating over that channel;

enabling one of the serial channels;

receiving data serially into the interface circuit at the selected compatible baud rate, the data being sent from one of the peripheral devices; and

communicating the data from the interface circuit to the CPU.