Logic circuit for an automatic braking system for a motor vehicle

• US 4,053,026 A
• Filed: 12/08/1976
• Issued: 10/11/1977
• Est. Priority Date: 12/09/1975
• Status: Expired due to Term

• Current Assignee: Nissan Motor Co., Ltd.
• Original Assignee: Nissan Motor Co., Ltd.
• Inventors: Endo, Hiroshi, Fujiki, Norio
• Primary Examiner(s): Blix, Trygve M.
• Assistant Examiner(s): Eisenzopf, Reinhard J.
• Application Number:
  US05/748,701
• Time in Patent Office: 307 Days
• Field of Search: 303/91, 303/93, 180/98, 343/112 CA, 343/7 VM, 343/7 VC, 340/52 H, 340/53, 340/258 R, 340/258 D
• US Class Current: 180/169
• CPC Class Codes: B60K 31/0008 including means for detecting potential obstacles in vehicle path
• CPC Class Codes: B60K 31/10 and means for comparing one electrical quantity, e.g. voltage, pulse, waveform, flux, or the like, with another quantity of a like kind, which comparison means is involved in the development of a pressure which is fed into the controlling means
• CPC Class Codes: B60T 2201/022 Collision avoidance systems
• CPC Class Codes: G01S 13/931 of land vehicles
• CPC Class Codes: G01S 2013/93185 Controlling the brakes
• CPC Class Codes: G01S 2013/93271 in the front of the vehicles

Abstract

Braking of a vehicle is prolonged by an improved logic circuit for a time or a distance to overcome stop starting braking due to momentary "safe" signals caused by multiple reflection of a radar signal.

Claims

1. In an automatic braking system for a motor vehicle having a brake for braking the vehicle which is applicable by the automatic braking system;

an antenna for transmitting and receiving a radar signal;

a radar operatively connected to the antenna;

a comparator a first input of which is connected to a first output of the radar to receive a first signal therefrom;

a square law demodulator the input of which is connected to the second output of the radar to receive a second signal therefrom;

a digital potentiometer connected to the square law demodulator to receive a third signal therefrom and arranged to increase the magnitude of the third signal by a coefficient to form a fourth signal, the output of the digital potentiometer being connected to a second input of the comparator to feed the fourth signal thereto, the comparator being arranged to compare the first and fourth signals and generate first and second logic signals;

a brake actuator driving circuit which is arranged to produce a drive signal in response to the first logic signal; and

a brake actuator connected to the brake actuator driving circuit to apply the brake of the vehicle when receiving the drive signal;

the improvement comprising

means connected between the output of the comparator and the input of the brake actuator driving circuit which adds the first logic signal to the input of the brake actuator driving circuit for a time after the first logic signal has disappeared from the output of the comparator.

2. An automatic braking system as claimed in claim 1, wherein said means comprises:

a monostable multivibrator, the input of which is connected to the output of said comparator and which is arranged to enter a quasi stable state for a period of time when a first logic signal disappears from the output of the comparator and to generate a first logic signal on its output while it is in the quasi stable state; and

an OR gate the first input of which is connected to the output of the comparator, the second input of which is connected to the output of the monostable multivibrator and the output of which is connected to the input of said brake actuator driving circuit.

3. An automatic braking system for a motor vehicle as claimed in claim 1 wherein said means comprises:

a differentiating circuit the input of which is connected to the output of said comparator and which is arranged to generate a set signal when the first logic signal disappears from the output of the comparator and the second logic signal appears on same;

a first means the first input of which is connected to the output of the differentiating circuit for receiving the set signal therefrom and which is arranged so that a first logic signal appears on its output when the set signal is received from the differentiating circuit;

a timing circuit the input of which is connected to the output of the first means and the output of which is connected to a second input of the first means, the timing circuit being arranged to generate a reset signal, which when received by the first means cause a second logic signal to appear on the output of the first means, for a predetermined time after being triggered by the presence of a first logic signal on the output of the first means, the predetermined time being variable with respect to the wheel speed of the vehicle in which the automatic braking system is mounted; and

an OR gate the first input of which is connected to the output of the comparator the second input of which is connected to the output of the first means and the output of which is connected to said brake actuator driving circuit.

4. An automatic braking system for a motor vehicle as claimed in claim 1 wherein said means comprises;

a differentiating circuit, the input of which is connected to the output of the comparator;

a flip-flop circuit the set input of which is connected to the output of the differentiating circuit;

an OR gate one input of which is connected to the output of the comparator and the other input of which is connected to the output of the flip-flop circuit;

an AND gate one input of which is connected to the output of the flip-flop;

a digital counter the input of which is connected to the output of the AND gate and the input of which is connected to the reset input of the flip-flop circuit; and

a pulse generator connected to the other input of the AND gate, the pulse counter being arranged to generate a train of pulses proportional to the wheel speed of the vehicle in which the automatic braking system is mounted.

5. An automatic braking system for a motor vehicle as claimed in claim 4 wherein said digital counter is a nine bit binary counter which is arranged to generate the said reset signal after counting through half a normal cycle.