Method of gettering using backside polycrystalline silicon

• US 4,053,335 A
• Filed: 04/02/1976
• Issued: 10/11/1977
• Est. Priority Date: 04/02/1976
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Hu, Shih-Ming
• Primary Examiner(s): Rutledge, L. Dewayne
• Assistant Examiner(s): Saba, W. G.
• Application Number:
  US05/672,906
• Time in Patent Office: 557 Days
• Field of Search: 148/1.5, 148/174, 148/175, 156/612, 357/52, 357/59, 357/64, 427/82, 427/86
• US Class Current: 438/143
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/31616 Deposition of Al2O3
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
• CPC Class Codes: H01L 21/3221 of silicon bodies, e.g. for gettering
• CPC Class Codes: Y10S 148/037 Diffusion-deposition
• CPC Class Codes: Y10S 148/06 Gettering
• CPC Class Codes: Y10S 148/085 Isolated-integrated
• CPC Class Codes: Y10S 148/122 Polycrystalline
• CPC Class Codes: Y10S 257/928 with shorted PN or schottky junction other than emitter junction

Abstract

An integrated circuit structure and method for manufacturing same which provides for gettering with a backside layer of polycrystalline silicon. The gettering of unwanted impurities from the integrated circuits involves the deposition of a polycrystalline silicon film on a semiconductor wafer prior to any or some high temperature processing steps. The semiconductor body is then subjected to the normal semiconductor processing steps to form semiconductor devices on the surface opposite to the surface having the polycrystalline silicon layer. During these high temperature processing steps, unwanted impurities such as copper, iron, nickel, sodium and potassium ions move toward and into the polycrystalline silicon layer and thereby away from the semiconductor devices. This produces improved yield in the integrated circuit process.

Claims

1. The method for gettering impurities and for removal of point defects from silicon semiconductor material comprising:

providing a body of monocrystalline silicon material suitable for forming semiconductor devices therein;

depositing a layer of polycrystalline silicon on one major surface of said body by hydrogen reduction of a silicon-containing gas which is passed over said body along with a inert carrier gas while said body is maintained at a temperature between about 600°

C. to 800°

C.;

said layer being predominently oriented to one crystallographic orientation; and

forming semiconductor devices on the major surface opposite to the said one major surface of said body which involve processing temperatures between about 800°

C. to 1100°

C.

2. The method of claim 1 wherein the temperature for depositing said layer is between about 680°

C. and 800°

C. and the thickness of said layer being between about 5000 A and 50000 A.

3. The method of claim 1 wherein a substantially contaminant impervious film is deposited over said layer of polycrystalline silicon.

4. The method of claim 3 wherein said film is amorphous silicon nitride.

5. The method of claim 3 wherein a silicon dioxide layer is formed on said layer of polycrystalline silicon before depositing said silicon nitride film.

6. The method of claim 3 wherein the said impervious film is aluminum trioxide.

7. The method of claim 3 wherein the said impervious film is amorphous silicon oxynitride.

8. The method of claim 3 wherein the thickness of said impervious film is between about 300 Angstroms and 2000 Angstroms.

9. The method of claim 1 wherein said semiconductor devices are metal oxide silicon field effect transistors.

10. The method of claim 3 wherein said body is silicon and one of the steps in forming said semiconductor devices includes the formation of an epitaxial silicon layer.

11. The method of claim 1 wherein the orientation of said body is (011) and the orientation of said layer is predominently [110] and average grain size of less than about 1 micrometer.