Band compression device
First Claim
1. A band compression device for receiving input signals of predetermined frequency bandwidth and for delivering output signals of bandwidth n times narrower comprising:
- sampling means for sampling said input signals;
storing means for storing at least two successive samples in a series of n successive samples;
amplitude comparing means for comparing said samples taken in pairs and for providing a logic transfer control signal depending on each of said amplitude comparisons;
an output memory for receiving the sample greatest in amplitude in said series and delivering said output signal; and
control means connected to said storing means, said output memory and receiving said logic control signal for transferring said greatest of the compared samples to said output memory.
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Accused Products
Abstract
The disclosure relates to band compression devices. The input signals are sampled and stored in at least two memories. In a sequence of n samples, two samples are taken in pairs, compared and the greatest of them is transferred to an output memory from which it can be read for a period equal to or less than the duration of the sequence. When using a non-shifting mode, the output memory is reset at the end of each sequence of n samples. A shifting mode is used in a device comprising a plurality of identical stages connected in series, where each new sample is transmitted to the next stage only if it is greater than the previous stored sample in each stage.
9 Citations
9 Claims
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1. A band compression device for receiving input signals of predetermined frequency bandwidth and for delivering output signals of bandwidth n times narrower comprising:
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sampling means for sampling said input signals; storing means for storing at least two successive samples in a series of n successive samples; amplitude comparing means for comparing said samples taken in pairs and for providing a logic transfer control signal depending on each of said amplitude comparisons; an output memory for receiving the sample greatest in amplitude in said series and delivering said output signal; and control means connected to said storing means, said output memory and receiving said logic control signal for transferring said greatest of the compared samples to said output memory. - View Dependent Claims (2, 3, 6)
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- 4. A band compression device comprising, in series, a first memory, second memory and an output memory, each memory having a sample control input, a comparator circuit connected to the input and output of the second memory for giving a control signal when the amplitude of the sample at the input of the second memory is greater than that of the sample at the output of said second memory, and control circuit means comprising, a clock circuit having an output, a delay circuit and a divider circuit having an output, said clock delay and divider being connected in series, said clock circuit having its output connected to the sampling control input of the first memory, said divider circuit having its output connected to the sampling control input of the output memory, and AND circuit having two inputs and its output connected to the sampling control input of the second memory, one of its inputs connected to the output of the delay circuit, and the other input connected to an OR circuit having its inputs connected respectively to the output of the comparator circuit and to the output of the divider circuit.
- 7. A band compression device for receiving input signals, comprising in series a plurality of identical stages, each stage comprising a memory, a two-input multiplexer and a comparator circuit having its inputs connected to the inputs of the multiplexer for applying to said multiplexer a control signal so that it will transmit the greatest of the two signals applied to its inputs, the output of the memory being connected to one input of the multiplexer, the other input receiving the input signals for the device, said input signals being also applied to the input of the memory of the first stage and the output of the multiplexer of each stage being connected to the input of the memory of the next stage, an output memory connected to the output of the multiplexer of the last stage and a clock circuit for applying sampling control signals to all memories of the device.
Specification