Silicon on sapphire MOS transistor

• US 4,053,916 A
• Filed: 09/04/1975
• Issued: 10/11/1977
• Est. Priority Date: 09/04/1975
• Status: Expired due to Term

• Current Assignee: Westinghouse Electric Corporation (Paramount Global (f/k/a ViacomCBS Inc.))
• Original Assignee: Westinghouse Electric Corporation (Paramount Global (f/k/a ViacomCBS Inc.))
• Inventors: Fitzpatrick, Michael D., Cricchi, James R.
• Primary Examiner(s): Wojciechowicz, Edward J.
• Application Number:
  US05/610,493
• Time in Patent Office: 768 Days
• Field of Search: 357/4, 357/23, 357/52, 357/86
• US Class Current: 257/353
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

An MOS transistor constructed using silicon on sapphire technology in which the channel region can be electrically connected either to the source or drain terminal is disclosed. The transistor is advantageous in that the shift of the threshold voltage of the transistor in the presence of radiation is substantially decreased. Connecting the channel region of the transistor to the source terminal also substantially reduces what is normally referred to as the "kink" effect in MOS transistors utilizing floating substrate channel regions. Reducing the sensitivity to radiation and the kink effect results in a transistor having improved electrical characteristics.

Claims

1. A planar transistor comprising

a. a semiconductive structure including:

1. a channel region of a first conductivity type interposed between drain and source regions of a second conductivity type,

2. at least one high conductivity region of said first conductivity type contiguous to said source and channel regions;

b. an insulating layer overlying said channel region;

c. an electrically conductive layer overlying said insulating layer to form the gate of said transistor;

d. electrically conductive means electrically coupled to said drain region to form the drain terminal of said transistor; and

e. electrically conductive means coupled to said source region and to said high conductivity region to form the source terminal of said transistor.

5. A transistor in accordance with claim 1 further including an insulating substrate on which said semiconductor structure is formed.

6. A transistor in accordance with claim 5 wherein said insulating substrate is sapphire.

7. A transistor in accordance with claim 1 wherein said first conductivity type is P.

8. A transistor in accordance with claim 1 wherein said first conductivity type is N.

2. A planar MOS transistor having gate, source and drain terminals comprising:

a. a semiconductive structure including;

1. drain and source regions of a first conductivity type,

2. a channel region of second conductivity type interposed between said drain and source regions,

3. at least one electrically conductive region of said second conductivity type forming a low resistance path to said channel region;

b. an electrically insulating layer overlying said channel region;

c. first electrically conductive means overlying said insulating layer to form the gate terminal of said transistor;

d. second electrically conductive means forming an electrically conductive path to said drain region to form said drain terminal;

e. third electrically conductive means coupled through a low resistance path to said source region and to said at least one electrically conductive region of said second conductivity type to form the source of said transistor.

3. A planar MOS transistor having a gate, source and drain terminals, comprising in combination;

a. a semiconductive structure supported on an electrically insulating substrate, said semiconductive structure comprising;

1. drain and source regions of a first conductivity type,

2. a channel region of a second conductivity type interposed between said drain and source region,

3. at least one electrically conductivity region of said second conductivity type forming a low resistance path to said channel region;

b. an electrically insulating layer overlying said channel region;

c. first electrically conductive means overlying said insulating layer to form said gate terminal;

d. second electrically conductive means coupled through a low resistance path to said drain region to form the drain terminal by said transistor; and

e. third electrically conductive means coupled through a low resistance path to said source region and to said at least one electrically conductive region of said second conductivity type to form the source terminal of said transistor.

9. A transistor in accordance with claim 3 further including a plurality of said regions of a second conductivity type.

10. A transistor in accordance with claim 9 wherein said plurality of regions of a second conductivity type are interdigitated with regions of said first conductivity type, said regions of said first conductivity type forming the source of said transistor.

4. A planar MOS transistor comprising a drain and source with a channel interposed therebetween:

a. a semiconductive structure comprising;

1. drain of a first conductivity type,

2. a region including alternating portions of said first conductivity type and a second conductivity type with said portions of said first conductivity type forming the source of said transistor with said portions of said second conductivity type forming a low resistance path to a channel region of said second conductivity type interposed between said drain and source regions;

b. an electrically insulating layer overlying said channel regon;

c. a first electrically conductive layer overlying said insulating layer to form a gate terminal of said transistor;

d. first electrically conductive means coupled through a low resistance path to said drain region to form the drain terminal of said transistor;

e. second electrically conductive means coupled to said source to form the source terminal of said transistor;

f. third electrically conductive means coupled to the portion of said region having said second conductivity type to provide a terminal coupled to said channel through a low resistance path.