Running average computer

• US 4,054,786 A
• Filed: 09/24/1973
• Issued: 10/18/1977
• Est. Priority Date: 09/24/1973
• Status: Expired due to Term

• Current Assignee: the united states of america as represented by the secretary of the navy
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Vincent, Allen E.
• Primary Examiner(s): Birmiel, Howard A.
• Application Number:
  US05/398,279
• Time in Patent Office: 1,485 Days
• Field of Search: 324/77 A, 235/156, 235/152, 235/180, 235/193, 340/3 R
• US Class Current: 702/199
• CPC Class Codes: G06F 17/18 for evaluating statistical data , e.g. average values, frequency distributions, probability functions, regression analysis forecasting specially adapted for a specific administrative, business or logistic context G06Q10/04

Abstract

A special purpose digital computer requiring minimal data storage capabil for continually calculating the numerical average of a predetermined number of sampled data values. The average I_n + 1 is calculated according to the equation: ##EQU1## WHEREIN I_n is the nth average stored; and

X_n + 1 is the (n + 1) sample input.

A new value for the average of all previously sampled data is calculated upon receipt of each new sample thereby eliminating the storing of past sampled data values. The prior calculated average is multiplied by the previous number of data samples and the product is added to a new sample. The resultant sum is divided by the sequence number of the new sample and the quotient, which represents the new average, is placed in data storage.

Claims

1. A signature recognition system for minimizing the effects of spurious variations of background noise, comprising, in combination:

analyzer means for periodically sampling the energy level in a frequency spectrum of an input signal for providing a digital output representative of the energy level within discrete frequency cells of said spectrum, and for providing a pulse at the beginning of each sampling period;

summing means having first and second inputs, said first input connected to receive said analyzer means output, and for providing an output representative of the sum of said first and second inputs;

dividing means having first and second inputs, said first input connected to receive the summing means output and providing an output representative of the average energy level of each of said foregoing cells;

storage means having an input connected to receive the dividing means output, and for providing an output representative of the average energy levels stored therein;

counting means connected to receive said pulse for providing an output indicative of the cumulative number of the sampling periods, said counting means output being connected to said dividing means second input; and

multiplying means having a first input connected to receive the storage means output, and a second input connected to receive said counting means output for providing an output representative of the product of the inputs, and said multiplying means output being connected to the summing means second input.

2. A digital processing system according to claim 1 wherein said dividing means further comprises:

an adder having an input connected to receive said dividing means second input and providing an output representative of a number one more than said second input; and

a divider having first and second inputs, said first input connected to receive said dividing means first input and said second input connected to receive the adder output for providing said dividing means output.

3. A digital processing system according to claim 2 wherein said analyzer means further provides a pulse signal at the beginning of each frequency cell.

4. A digital processing system according to claim 3 wherein said counting means output is zero for the first count.

5. A digital processing system according to claim 4 wherein said storage means is a recirculating shift register.

6. A digital process for averaging the energy levels of corresponding ones of a repetitive series of input signals, comprising, in combination:

summing means having first and second inputs, said first input for receiving respective ones of said input signals, and for providing an output representative of the sum of said first and second inputs;

dividing means having first and second inputs, said first input connected to receive the summing means output and providing an output representative of the average energy level of each of said input signals;

storage means having an input connected to receive the dividing means output, and for providing an output representative of the average energy levels stored therein;

counting means for receiving a pulse once each repetition of said series for providing an output indicative of the cumulative number of said repetitions, said counting means output being connected to said dividing means second input; and

multiplying means having a first input connected to receive the storage means output, and a second input connected to receive said counting means output for providing an output representative of the product of the inputs, and said multiplying means output being connected to the summing means second input.

7. A digital process according to claim 6 wherein said dividing means further comprises:

an adder having an input connected to receive said dividing means second input and providing an output representative of a number one more than said second input; and

a divider having first and second inputs, said first input connected to receive said dividing means first input and said second input connected to receive the adder output for providing said dividing means output.

8. A digital process according to claim 7 wherein said counting means output is zero for the first count.

9. A digital process according to claim 8 wherein said storage means is a recirculating shift register.